History of parallel computers, Computer Engineering

Assignment Help:

History Of Parallel Computers

The test with and implementations of the utilize of parallelism started year back in the 1950s by the IBM.  The IBM enlarges computers also called as IBM 7030 was building in 1959.  In the design of these computers, a number of new ideas like overlapping I/O with processing and instruction look ahead were established.  A serious advance towards designing similar computers was going ahead with the development of ILLIAC IV in 1964 at the University of Illinois.  It had an only control unit but have multiple processing elements. On this machine, at a time, a one operation is executed on dissimilar data items by diverse processing elements. The idea of pipelining was begin in computer CDC 7600 in 1969.  It takes pipelined arithmetic unit.  In the years 1970 to 1985, the study in this area was decided on the development of vector super computer.  In 1976, the CRAY1 was determined by Seymour Cray.  Cray1 was a pioneering effort in the enlargement of vector registers. It accessed main memory only for store and load operations. Cray1 never use optimized pipelined arithmetic unit and virtual memory.  Cray1 had timer speed of 12.5 n.sec. The Cray1 processor evolved upto a speed of 12.5 Mflops on 100 × 100 linear equation solutions. The next invention of Cray called Cray XMP was introduced in the years 1982-84.  It was attached with 8-vector supercomputers and it is used a shared memory also.

Apart from Cray, the giant company developing, Control Data Corporation (CDC), parallel computers of USA, formed supercomputers, the CDC 7600. Its vector supercomputers named Cyber 205 had memory to memory architecture that is, input Vector operands were flow from the main memory to the vector arithmetic unit and the outputs were accumulated back in the main memory.  The benefit of this architecture was that It did not maximize the size of vector operands. The drawback was that it essential required a very high speed memory so that there would be no speed mismatch between main memory and vector arithmetic units.  Developing such high speed memory is very expensive. The Clock hustle of Cyber 205 was 20 n.sec. In the 1980s Japan also going ahead for manufacturing high performance vector supercomputers. Companies like, Fujitsu, Hitachi and NEC were the core manufacturers.  Hitach Established S-810/210 and S-810/10 vector supercomputers in 1982. All these equipment used semiconductor technologies to accomplish speeds at par with Cyber and Cray.  But their vectorisers and operating system were inferior than those of American companies.


Related Discussions:- History of parallel computers

View the site files, To see a high-level representation of the structure of...

To see a high-level representation of the structure of a local site, you use Dreamweaver's Site Map view. You can also use site map to add new files to the site, to add, remove and

Advantages and drawbacks of mealy and moore machine, What are the advantage...

What are the advantages and drawbacks of mealy and moore machine? Advantages and drawbacks: Into Mealy as the output variable is a function both state and input, changes o

Select statements linked to a logical database, One cannot use SELECT state...

One cannot use SELECT statements in a report program linked to a Logical Database   False. You can use th SELECT statements.

Flynn’s classification, Flynn's Classification Flynn's classification i...

Flynn's Classification Flynn's classification is based on multiplicity of data streams and instruction streams observed by the CPU during program execution. Let Ds and Is  are

Finite automata, applications of context free grammar

applications of context free grammar

Syntax and semantics for first-order logic , Syntax and Semanticsx and Sema...

Syntax and Semanticsx and Semantics for First-order logic - artificial intelligence: Propositional logic is limited  in its expressiveness: it may just represent true and false

War (write after read) - data hazards , WAR (write after read) - Data hazar...

WAR (write after read) - Data hazards in computer architecture: WAR (write after read) - j tries to write at destination before it is read by i , hence i  wrongly gets the n

Difference between blocking and non-blocking, Difference between blocking a...

Difference between blocking and non-blocking Verilog  language  has  two  forms  of  the  procedural  assignment  statement:  blocking  and  nonblocking. The two are distinguis

Select-options and parameters statement , The fields specified by select-op...

The fields specified by select-options and parameters statement cannot be grouped together in the selection screen. No, the fields specified by select-options and parameters s

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd