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For JK flipflop J = 0, K=1, the output after clock pulse will be ? Ans. J=0 and K=1, such inputs will reset the flip-flop, after the clock pulse. Therefore whatever be the earlie
Mention the various IC logic families. Ans. Different IC Logic Families: Digital IC's are fabricated through employing either the Unipolar or the Bipolar Technologies and are te
find the minimum total number of shelves including the loading process
Half Adder (for addition of two bits) Full Adder (for addition of three bits) Carry look ahead adder Carry save adder Carry propagate adder
Companding helps in reducing with respect to signal: (A) Interference (B) Signal overloading (C) Non linearity (D) Quantization noise
Mathematical Simulation and Modelling Applications The tasks include mathematical simulation and modelling need lots of parallel processing. Three fundamental formalisms in mat
What is time out mechanism. If one unit is faulty the data transfer will not be done. Such an error can be detected using time out mechanism which makes an alarm if the data tr
Q. Explain Register Indirect Addressing? In this addressing technique the operand is data in memory pointed to by a register. Or we can say in other words that the operand fie
What are the techniques of Data Collection It can be either automatic or manual. Manual techniques can include: - Keypads/Keyboards to type in data - touch screens to s
Q. A. Which gates are called Universal Gates? Why? B. State and prove any one of the DeMorgen's Laws. Show that these theorems can be extended up to any number of variables.
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