a) Give four features that were traditionally reserved to RISC architectures?

b) Determine the overall throughput for 21 sequential instructions assuming a four-stage pipeline and each instruction goes through fetch (7 nanoseconds), decode (2 nanoseconds), execute (1nanosecond) and write-back (10 nanoseconds) stages?

c) Calculate the CPI for a hypothetical 1.8 GHz processor with a benchmarked rating of 500 MIPS?

d) Assume a processor with instruction frequencies and costs as follows

• Integer ALU: 50%, 2 cycles
• Load: 25%, 5 cycles
• Store: 10%, 3 cycles
• Branch: 15%, 2 cycles

Determine which of the following three cases will improve or reduce overall performance and by how much:

CASE 1: Reduce Branch cost to 1 cycle and Store cost to 2 cycles
CASE 2: Reduce Load cost to 3 cycles while increasing ALU cost to 4 cycles
CASE 3: Reduce Load cost to 4 cycles

e) Mention one advantage of using DMA over Interrupt-Driven I/O. Give the basic structure of a basic DMA module.