General terms for cache-microprocessor, Assembly Language

Assignment Help:

General terms for Cache :

Cache Hits : When the cache consisted the information requested, the transaction is said to be a cache hit.

Cache Miss : When the cache does not have the information requested, the transaction is said to be a cache miss.

Cache consistency : Since cache is a photocopy of a small piece main memory, it is essential that the cache always reflects what is in main memory.

Snoop : When a cache is watching the address lines for transaction, this is known a snoop.  This function permit thecache to see if any transactions are accessing memory it contains within itself.

Snarf : When a cache takes the information from the data lines, the cache is command to have snarfed the data.   This function permits the cache to be updated and maintain consistency.

Snoop and snarf are the mechanisms the cache utilize to maintain consistency.

Dirty Data : When data is modified within cache but not in main memory, the data in cache is called "dirty data."

Stale Data : When data is modified in main memory but not in cache, the data in the cache is called stale data.

Cache Architecture : Caches have 2 characteristics, a write policy anda read architecture. "The write policy might be either"Write-Through."Or "Write-Back". The read architecture can be either "Look Aside" or "Look Through.


Related Discussions:- General terms for cache-microprocessor

Pointer(ptr)-assemblers directive-microprocessor, PTR : Pointer:- The p...

PTR : Pointer:- The pointer operator which is used to declare the type of a variable, label or memory operand. The operator PTR is prefixed by either WORD or BYTE. If the prefi

Not-logical instruction-microprocessor, NOT : Logical Invert: The NOT inst...

NOT : Logical Invert: The NOT instruction complements (inverts) the contents of an a memory location or operand register bit by bit. The instance are as following: Example :

8254 programmable timer-microprocessor, 8254 Programmable Timer A diagr...

8254 Programmable Timer A diagram of Intel's 8254 interval event/timer counter is given in Figure. The 8254 consists of 3 identical counting circuits, per of which has GATE and

Program to move contents in memory-machine level programs, Example : Write...

Example : Write a program to move the contents of the memory location 0500H to BX and also to register CX. Add immediate byte 05H to the data residing in memory location, whose ad

Intel 8259 interrupt controller-microprocessor, Intel 8259 interrupt contro...

Intel 8259 interrupt controller :  The 8088 processor has only two interrupt control inputs, and interrupt request (INTR) and non mask able interrupt (NMI). NMI are interrupts t

Al registre, check the al-register for palindromic number

check the al-register for palindromic number

Code, 1. Assembly code for the flow chart we did in the class about the sim...

1. Assembly code for the flow chart we did in the class about the simple I/O interface driver 2. Enhanced driver (flow chart and its assembly code) to cater for interruptions in th

8086, to separate positive and negative numbers

to separate positive and negative numbers

Addsub, Using the AddSub program from Ch3 under c:\Masm615\examples as a re...

Using the AddSub program from Ch3 under c:\Masm615\examples as a reference, write a program that subtracts three 16-bit integers using only registers. Insert a call DumpRegs statem

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd