Floating point arithmetic pipelines, Computer Engineering

Assignment Help:

Floating point Arithmetic pipelines

Floating point computations are the finest candidates for pipelining. Take the instance of addition of two floating point numbers. Following phases are identified for the addition of two floating point numbers:

  • First phase will compare the exponents of the two numbers.
  • Second phase will look for alignment of mantissas.
  • Third phase, mantissas are added.
  • In the last phase, the result is normalized.

These phases are given below:-

                                         1393_Floating point Arithmetic pipelines.png

                                            Arithmetic Pipeline for Floating point addition of two numbers


Related Discussions:- Floating point arithmetic pipelines

What is bank interleaving, Interleaved memory is a method for compensating ...

Interleaved memory is a method for compensating the relatively slow speed of DRAM. The CPU can access alternative sections instantly without waiting for memory to be cached. Multip

Performance and issues in pipelining-speedup, Performance and Issues in Pip...

Performance and Issues in Pipelining Speedup:   Firstly, we get the speedup factor that is we see how much speed up performance we get through pipelining. First we get the

Full resolution rule - artificial intelligence, Full Resolution Rule - Arti...

Full Resolution Rule - Artificial intelligence: Now that we know about unification, we can correctly describe the complete edition of resolution: p1  ∨ ...  ∨ pj  ∨ ...  ∨ p

What are the static and dynamic hazards in logic circuits, If for a short p...

If for a short period of time circuits goes to some dissimilar logic level then it is assumed to have then it is known as static hazard e.g. If the final logic value of output of a

Explain wait for graph-resource request and allocation graph, Explain Wait ...

Explain Wait for graph (WFG) with Resource request and allocation graph (RRAG). WFG with RRAG: A graph G = (V,E) is termed as bipartite if V can be decomposed in two

Determine what is the frame rate and frame duration, (i)  A multiplexer com...

(i)  A multiplexer combines four 100-Kbps channels using a time slot of 4 bits. Each Frame has the size of 16 bits. a)  Show the output with the four inputs as shown in the figu

Identify state as shifting register content to left by 1 bit, Shifting a re...

Shifting a register content to left by one bit position is equivalent to ? Ans. Multiplication by two is equivalent while shifting register content to left by one bit position.

What is a multiplexer tree, What is a Multiplexer Tree? Ans Multip...

What is a Multiplexer Tree? Ans Multiplexer Tree: The largest available MUX IC is 16 to 1. Meeting the larger input requires there must be a provision to expand this. It

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd