Explain XLAT instruction with help of example, Computer Engineering

Assignment Help:

Q. Explain XLAT instruction with help of example?

Let's presume a table of hexadecimal characters signifying all 16 hexadecimal digits in table:

HEXA      DB      '0123456789ABCDEF'

760_Explain XLAT instruction with help of example.png

The table comprises the ASCII code of every hexadecimal digit:

(All value in hexadecimal)

If we place 0Ah in AL with the thought of converting it to ASCII we have to set BX to offset of HEXA and invoke XLAT.  You need not specify table name with XLAT hence it is implicitly passed by setting BX to HEXA table offset. This instruction would do the subsequent operations:

It will first add AL to BX producing an effective address which points to eleventh entry in the HEXA table.

Content of this entry is now moved to AL register which means 41h is moved to AL. 

Or we can say in other words, XLAT sets AL to 41h since this value is located at HEXA table offset 0Ah. Please consider that 41h is the ASCII code for hex digit A. The subsequent sequence of instructions will accomplish this:

MOV AL, 0Ah    ; index value

MOV BX, OFFSET HEXA; offset of the table HEXA

XLAT     

The above tasks can be executed without XLAT instruction however it will need a long series of instructions like:

MOV AL, 0Ah                                   ; index value

MOV   BX, OFFSET HEXA             ; offset of the table HEXA

PUSH BX                                           ; save the offset

ADD BL, AL                                     ; add index value to table

                                                                        ; HEXA offset

MOV   AL, [BX]                                ; retrieve the entry

POP    BX                                           ; restore BX


Related Discussions:- Explain XLAT instruction with help of example

Explain the term step-wise refinement, Explain the term step-wise refinemen...

Explain the term step-wise refinement. Ans:  Step Wise Refinement  Refinement is a method of elaboration. Here one starts with a statement of function that is described a

What are the requirements a dialog program must fulfill, What are the requi...

What are the requirements a dialog program must fulfill? A dialog program must fulfil the following requirements A user friendly user interface. - Format and consistency

What is basic time division switching, What is Basic Time Division Switch...

What is Basic Time Division Switching? Basic Time Division Switching: The functional blocks of a memory based time division switching switch is demonstrated in figure and i

Uniform memory access model (uma), Uniform Memory Access Model (UMA) In...

Uniform Memory Access Model (UMA) In this model, the main memory is uniformly shared by all processors in multiprocessor systems and each processor has equal access time to sha

Explain pipelining, Define pipelining Pipelining is an efficient way of...

Define pipelining Pipelining is an efficient way of organizing concurrent activity in a computer system. The processor implements the program by fetching and implementing instr

How free-space is managed using bit vector implementation, How free-space i...

How free-space is managed using bit vector implementation? The free-space list is executed as a bit map or bit vector. Each block is shown by 1 bit. If the block is free, the b

Disc shapes and diameters - computer architecture, Disc shapes and diameter...

Disc shapes and diameters:     A Mini-CD is 8 centimeters in diameter. The digital data on a CD start at the center of the disc and proceeds toward the edge, whi

State of the register, What is the state of the register in Figure  after e...

What is the state of the register in Figure  after every clock pulse if it begins in the 101001111000 state?

Calculate the switching elements in a two stage network, In a two stage ne...

In a two stage network there are 512 inlets and outlets, r=s=24. If the probability that a given inlet is active is 0.8, calculate: the switching elements Given: N =M =512,

Address phase timing - computer architecture, Address phase timing: On...

Address phase timing: On the rising edge of clock 0, the initiator notes IRDY # and FRAME# both high, and GNT# low, so it drives the command, address and asserts FRAME# in tim

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd