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Q. Explain working of D Flip -Flop?
D (data) flip-flop is modification of RS flip-flop. Problem of undefined output in SR flip-flop when both R and S become 1 gets avoided in D flip-flop. The easy solution to prevent such condition is by providing only a single input. So non-clocked inputs to AND gates (S and R of fig (b)) are guaranteed to be opposite of each other by inserting an inverter amid them. The logic figure and characteristic table of D flip flop is displayed in figure below.
Figure: D Flip flop
D flip-flop is also known as Delay flip-flop since it delays 0 or 1 applied to its input by a single clock pulse.
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