Using D-Flip flops and waveforms explain the working of a 4-bit SISO shift register.

Ans. Serial In-Serail Out Shift Register: Fig.(a) demonstrates a 4 bit serial in-serial out shift register having four D flip flops FF₀ , FF₁ , FF₂ and FF₃. As demonstrated it is a positive edge triggered device. The working of such register for the data 1010 is specified in the subsequent steps.

1. Bit 0 is entered in data input line. D₀ = 0, primary clock pulse is applied, FF₀ is reset and stores 0.
2. Subsequently bit 1 is entered. Q₀ = 0, as Q₀ is linked to D₁, D₁ becomes 0.
3. Then second clock pulse is applied, the 1 upon the input line is moved or shifts into FF₀ since FF₀ sets. The 0 that was stored in FF₀ is moved into FF₁.
4. Subsequently bit 0 is entered and third clock pulse applied. 0 is goes into FF0, 1 stored in FF0 is shifts to FF₁ and 0 stored in FF₁ is shifts to FF₂.
5. Final bit 1 is entered and 4th clock pulse applied. 1 is goes into FF₀, 0 stored in FF₀ is shifts to FF₁, 1 stored in FF₁ is shifts to FF₂ and 0 stored in FF₂ is shifts to FF₃.
This finishes the serial entry of 4 bit data in the register. Then the LSB₀ is on the output Q₃.
6. Clock pulse 5 is then applied. LSB₀ is shifted out. The subsequent bit 1 shows on Q₃ output.
7. Clock pulse 6 is then applied. The 1 on Q₃ is shifted out and 0 appears on Q₃ output.
8. Clock pulse 7 is then applied. 0 on Q₃ is shifted out. Here 1 shows on Q₃ output.
9. Clock pulse 8 is then applied. 1 on Q₃ is shifted out.
10. While the bits are being shifted out (upon CLK pulse 5 to 8) extra data bits can be entered in.