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Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times drive driving a net with a fan out of 3, with a total load capacitance (comprising the input capacitance of the three driven cells plus the interconnect) of 0.15pF. Assume the cell is fabricated using the Compass 0.5 micronmeter technology (C5) with parameters given in Table p133 (Smith).
Calculate power delivered to the network: 1. A wave is traveling from left to right, emerging from Z g =50 with a peak amplitude of V p =5V. The 1-port network [S] has in=0.5-
Using Bode plot calculate (a) Phase margin (b) Gain margin (c) Stability of closed loop system. The open transfer function of the system is t=30/(s+2)/(s+3)Using Bode plot calcula
Geometric transformations Apply the following geometric transformation to a set of points. Generate randomly coordinates for 1 point X=(x,y). X=100*rand(2,1) x=X(1,1)%to
Calculate Voltage and Current Phasors on a Phasor Diagram A synchronous motor is operated at rated load and unity power factor. The field current is increased by 20%. Show the
Design a circuit using op-amp that will reject the 60kHz power line noise and also reject high signal frequency above 800Khz. The stop-band width around the 60kHz centre frequency
Q. Explain working of TTL NAND gate? The TTL logic family uses only transistors instead of a combination of transistors and diodes. TTL has the same high and low ranges as DTL.
What is USB? USB: The USB (UNIVERSAL SERIAL BUS) is intended to join peripheral devices as keyboards, modems, a mouse and sound cards to the microprocessor by a serial data pat
sketching of wire 1 is charged and wire 2 uncharged
Q. Show that the block diagram of Figure can be reduced to the form of Figure. Find G eq (s) and H eq (s).
Q. Which Steps are used for the procurement? a. Initially, an introductory letter may be sent addressed to The Head, NRSA Data Centre, National Remote Sensing Agency, Balanagar
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