Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times drive driving a net with a fan out of 3, with a total load capacitance (comprising the input capacitance of the three driven cells plus the interconnect) of 0.15pF. Assume the cell is fabricated using the Compass 0.5 micronmeter technology (C5) with parameters given in Table p133 (Smith).
Pareto Analysis Pareto charts are based on the principle - "Vital Few Trivial Many". It allows user to focus attention on a few significant factors in a process. It is very us
A 3-kVA, 220:110-V, 60-Hz, single-phase transformer yields these test data: • Open-circuit test: 200 V, 1.4 A, 50 W • Short-circuit test: 4.5 V, 13.64 A, 30 W Determine th
Give the applications of PVC. PVC- It is acquired from polymerisation of hydrogen chloride and acetylene in the presence of a catalyst as peroxides at about 50 0 C. It is e
Name the various magnetically hard alloys. Several of the magnetically hard materials are rare earth carbon steel, cobalt, tungsten steel, alnico, hard ferrites and cobalt stee
Why memory decoding is required? To attach a memory device to the microprocessor, this is necessary to decode the address sent by the microprocessor. Decoding creates the memo
Write some disadvantages of loosely coupled systems More complicated due to the needed additional communication hardware. They are less portable and more expensive because o
Define the DMA controller interface. A DMA controller interfaces along with a few peripherals which may request DMA. The controller chooses the priority of simultaneous DMA req
Q. What are multistageand single stage networks? Compare strengths and weaknesses of each. OR List the key difference in single stage, two stage and three stage Networks. A
Q. Consider the circuit of Figure with V S = 94 V, V Z = 12 V, R = 820 , R L = 220 , R S = 0, and R Z = 25 . Assume the reverse saturation current of the zener diode to be
Referring to Figure, let boxes 2, 3, and 5 consist of a 0.2-H inductor, a 5- resistor, and a 0.1-F capacitor, respectively. Given A = 5, and v 1 = 10 sin 10t, i 2 = 5 sin 10t ,
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd