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Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times drive driving a net with a fan out of 3, with a total load capacitance (comprising the input capacitance of the three driven cells plus the interconnect) of 0.15pF. Assume the cell is fabricated using the Compass 0.5 micronmeter technology (C5) with parameters given in Table p133 (Smith).
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Q. If the line of Problem 15.1.3 is made of copper whose resistivity ρ = 1.72×10 -8 ·m, determine the maximum length that can be used if losses are not to exceed 3 dB when f = 3
Working and block diagram
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