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Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times drive driving a net with a fan out of 3, with a total load capacitance (comprising the input capacitance of the three driven cells plus the interconnect) of 0.15pF. Assume the cell is fabricated using the Compass 0.5 micronmeter technology (C5) with parameters given in Table p133 (Smith).
What do you understand by ASSUME assembler directive? ASSUME: This directive will be utilized to map the segment register names along with memory addresses. The Synta
State the Advantages of expert systems - Never "forgets" to ask a question in determining the logic - provides consistent answers - Less skilled work force needed, ther
a) Illustrate the Schematic diagram of the Transformer Box used in the Practical Session b) Calculate the output voltage on an Oscilloscope and determine its amplitude and freq
Q. (a) Determine the voltage at A in Figure . (b) With V i = 10 V, R 1 = 10 k, R 2 = 1000 , and A = 100, find the current i .
please explain phasor diagram and equivalent circuit
Q. Transistor terminals in BJT ? BJTS have three terminals namely base terminal, emitter terminal and collector terminal .The emitter layer is a source of charge carriers and i
Externally Initiated Signals Other than interrupt there are followings externally initiated signals available in 8085 microprocessor.
Q. ADMM (digital multi meter) reads true rms values of current. If the peak value of each of the following periodic current waves is 5 A, find the meter reading for: (a) a sine wav
Q. Write a short note on types of enclosure of machine. Sol. The various types of d.c. machine : (1) Magnetic frame or Yoke (2)
Q. Determine the voltages Vx using voltage division and equivalent resistor reductions for the circuits shown in Figure.
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