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Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times drive driving a net with a fan out of 3, with a total load capacitance (comprising the input capacitance of the three driven cells plus the interconnect) of 0.15pF. Assume the cell is fabricated using the Compass 0.5 micronmeter technology (C5) with parameters given in Table p133 (Smith).
Shunt DC motor In this arrangement, the armature and field coils are connected in parallel (the motor is called 'shunt connected'). Analysis With refere
Q. An n-channel JFET is given to have V P = 3V and I DSS = 6 mA. (a) Find the smallest value of v DS when v GS =-2 V if the operation is to be in the active region. (b) D
Q. The 50-turn coil in the configuration of Figure is rotated at a constant speed of 300 r/min. The axis of rotation is perpendicular to a uniform magnetic flux density of 0.1 T. T
explain dynamically induced emf and derive expression for it
Explain the principle of induction applied in electrical machine
Q. Three loads in parallel are supplied by a single phase 400-V, 60-Hz supply: Load A: 10 kVA at 0.8 leading power factor Load B: 15 kW at 0.6 lagging power factor Load C:
The free electron theory of metals was first proposed by Drude and later improved by Lorentz. The main postulates of this theory are 1. All metal contain, adequate number
Q. Three single-phase, 10-kVA, 2400/120-V, 60- Hz transformers are connected to form a three- phase, 4160/208-V transformer bank. Each of the single-phase transformers has an equiv
With neat diagrams explain the configuration of a step-by-step switching system. Schematic diagram for such an exchange is given in Figure. Every subscriber is connected to a
Q. Draw the developed diagram of a simplex progressive 2 layer lap winding for a 4 pole generator with 12 coils clearly indicating the position of brushes. Sol. No. o
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