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Explain the architecture of SS7.
A block schematic diagram of the CCITT no. 7 signaling system is demonstrated in figure.
Signal messages are passed by the central processor of the sending exchange to the CCS system. It consists of the microprocessor depends subsystem.
The signaling termination subsystem, the error control subsystem and the signaling control subsystems. The signaling control subsystem formations the messages in the suitable format and queues them for transmission. While there are no messages to send, this generates filler messages to remain the link active. Messages after that passed to the signaling termination sub-system, here whole signal units (SU) are assembled BY using sequence numbers and check bits generated through the error control subsystem. On the receiving terminal, the reverse sequence is continued. The levels are given below as:
Level 1: The Physical Layer
Level 2: The Data Link Level
Level 3: The signaling network level
Level 4: The User Part
FIG - Block Schematic Diagram of CCITT No.7 Signally System
Describe the Hardwired control method for generating the control signals Hard-wired control can be explained as sequential logic circuit that generates particular sequences of
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