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Q. Explain Status and Control Registers?
For control of numerous operations several registers are used. These registers can't be used in data manipulation though content of some of these registers can be used by programmer. One of the control registers for a von-Neumann machine is the Program Counter (PC).
Almost all the CPUs have a status register a part of which may be programmer visible. A register that may be formed by condition codes is called condition code register. Some of the commonly employed flags or condition codes in such a register may be:
These flags are set by CPU hardware while performing an operation. For illustration an addition operation can set overflow flag or on a division by 0 the overflow flag can be set etc. These codes can be tested by a program for a typical conditional branch operation. Condition codes are collected in one or more registers. RISC machines have various sets of conditional code bits. In these machines, an instruction specifies the set of condition codes that is to be used. Independent sets of condition code allow provisions of having parallelism within the instruction execution unit.
Flag register is frequently called as Program Status Word (PSW). It comprises condition code and other status information. There can be numerous other status and control registers like interrupt vector register in machines employing vectored interrupt or stack pointer if a stack is used to implement subroutine calls etc.
Instruction Set Architecture (ISA): The Instruction Set Architecture (ISA) is the part of the processor which is noticeable to the compiler writer or programmer. The ISA serve
Dynamic address translation : If, when executing an instruction, a CPU fetches an instruction located at a specific virtual address, or fetches data from a particular virtual
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