Explain SR Latch with NAND Gate?

SR Latch has two useful states:

• Set state, when output Q=1 and Q'=0.
• Reset state, when output Q=0 and Q'=1.Output Qand Q' are normally complement of each other.

• Undefined state, when Q=1 and Q'=1, occurred when both inputs R and S are equal to 0 at the same time.
• Under normal conditions, both inputs of the latch (Rand S) remain at 1 unless the state has to be changed.
• To let latch in the set state, Smust be 0
• To let latch in the reset state, Rmust be 0
• The inputs Sand Rmust go back to 1 before any other changes to avoid the occurrence of the undefined state (when Q=1 and Q'=1)
• The latch go to the set state or reset state and stay there even after both inputs return to 1.