Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Explain Space Switching.
Space Switches: Connections can be made in between outgoing and incoming PCM highways by a cross point matrix of the form demonstrated in figure. However, various channels of an incoming PCM frame may require to be switched by various cross points in order to reach various destinations. Therefore, the cross point is a two-input AND gate. One input is linked to the incoming PCM highway and another to a connection store which produce a pulse at the needed instant. A group of cross points gates can be implemented like an integrated circuit, for illustration using a multiplexer chip.
FIG - Space Switch.
Figure demonstrates a space switch with k incoming and m outgoing PCM highways, all carrying n channels. The connections store for every column of cross points is a memory along with an address location for every time-slot that stores the number of the cross points to be operated in which time slot. This number is written in the address by the controlling processor so as to setup the connection. The numbers are read out cyclically, into synchronism along with the incoming PCM frame. In every time slot, the number stored at the equivalent store address is read out and decoding logic converts it in a pulse or a single lead to function the relevant cross point.
Because a cross point can make a diverse connection in each of the n time-slots, this is corresponding to n cross points in a space division network. The total space switch is therefore equivalent to n separate k x m switches in a space division switching network.
Zero address instruction format is used for (A) RISC architecture. (B) CISC architecture. (C) Von-Neuman architecture. (D) Stack-organized architecture.
Q. Define about Hyper-threading technology? Hyper-threading technology enables a single microprocessor to behave as two separate threaded processors to operating system and app
Differentiate the latch and flip-flop? The major difference between latch and FF is which latches is level sensitive whereas FF is edge sensitive. They both need the use of clo
If you are using C language to implement the heterogeneous linked list, what pointer type will you use? The heterogeneous linked list having different data types in its nodes a
Define cache memory? A special very high speed memory known as a cache is sometimes used to increase the speed of processing by making current programs and data available to th
a. What is the meaning of user interaction? What are the dissimilar styles in which forms of interaction can be classified? Give one advantage, disadvantage and an example of every
Show System call for cloning. Standard form of Clone function is as follows: Int clone (Int (*FN) (), void *child stack, Int flag, intargs,); Parameter FN is Pointer fro
Q. Explain Redundant Array of Independent Disks levels? One such industrial standard that exists for multiple-disk database schemes is called as RAID which implies Redundant Ar
Flag is known as Low order register & Accumulator is known as High order Register.
You have a file having sporting goods that are sold online. Every item record contains the item id, item name, item description, item category, item price, and the units in stock.
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd