Explain space switching, Computer Engineering

Assignment Help:

Explain Space Switching.

Space Switches: Connections can be made in between outgoing and incoming PCM highways by a cross point matrix of the form demonstrated in figure. However, various channels of an incoming PCM frame may require to be switched by various cross points in order to reach various destinations. Therefore, the cross point is a two-input AND gate. One input is linked to the incoming PCM highway and another to a connection store which produce a pulse at the needed instant. A group of cross points gates can be implemented like an integrated circuit, for illustration using a multiplexer chip.

879_Space Switch.png

FIG - Space Switch.

Figure demonstrates a space switch with k incoming and m outgoing PCM highways, all carrying n channels. The connections store for every column of cross points is a memory along with an address location for every time-slot that stores the number of the cross points to be operated in which time slot. This number is written in the address by the controlling processor so as to setup the connection. The numbers are read out cyclically, into synchronism along with the incoming PCM frame. In every time slot, the number stored at the equivalent store address is read out and decoding logic converts it in a pulse or a single lead to function the relevant cross point.

Because a cross point can make a diverse connection in each of the n time-slots, this is corresponding to n cross points in a space division network. The total space switch is therefore equivalent to n separate k x m switches in a space division switching network.


Related Discussions:- Explain space switching

What is an interpreted languages, What is an interpreted languages In ...

What is an interpreted languages In interpreted languages, the instructions are implemented immediately after parsing. Both tasks are done by the interpreter. The code is sav

Meaning of every field in mips instruction, Q. Meaning of every field in MI...

Q. Meaning of every field in MIPS instruction? The meaning of every field in MIPS instruction is given below: op: operation code or opcode rs: First register source

Determine the nand gate, Find out the two inputs when the NAND gate output ...

Find out the two inputs when the NAND gate output will be low. Ans. The output of NAND gate will be low if the two inputs are 11. The Truth Table of NAND gate is shown

Explain about merge sort circuit, Q. Explain about Merge sort circuit? ...

Q. Explain about Merge sort circuit? First split the given sequence of n numbers in two parts every part comprising of n/2 numbers. Afterwards recursively divide the sequence i

Determine a sample rate required for telephone conversation, A sample rate ...

A sample rate of            is required for a good quality representation of telephone conversation. A sample rate of 50 times/second /mile of distance travelled are needed fo

Explain stored program control, Explain Stored Program Control. Stored...

Explain Stored Program Control. Stored Program Control: Modern digital computers utilize the stored programmed idea. Now, a program or a set of instructions to the computer i

What is sensitivity list, What is sensitivity list? A list of signals w...

What is sensitivity list? A list of signals which trigger execution of the block when they change value. Sensitivity list  indicates that when a change occurs to any one of

Explain about mainframes computer, Q. Explain about Mainframes computer? ...

Q. Explain about Mainframes computer? Mainframes, capable of executing in excess of 53 MIPS, are high-performance, general- purpose computers supporting very large databases, r

What is difference between cobol and vs cobol ii, In using COBOL on PC we h...

In using COBOL on PC we have only flat files and the programs can access only limited storage, while in VS COBOL II on M/F the programs can access up to 16MB or 2GB depending on th

What is graceful degradation, What is graceful degradation? In multipro...

What is graceful degradation? In multiprocessor systems, failure of one processor will not halt the system, but only slow it down by sharing the work of failure system by other

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd