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Nodal analysis procedure:
1. Verify the number of common nodes and reference node within the network.
2. Assign current and its direction to every distinct branch of the nodes in the network.
3. Apply KCL at each of the common nodes in the network
4. Solve the resulting simultaneous linear equation for the nodal voltages.
5. Determine the currents through and voltages across each the elements in the network.
Q. What happens when a negative bias is applied to the gate of a FET? The result of applying a negative bias to the gate is to reach the saturation level at a lower level of V
explain about heat time curve and cool time curve
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