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Multiple Instruction and Single Data stream (MISD): In this type of organization multiple processing elements are ordered under the control of multiple control units. Every control unit is managing one instruction stream and processed by its consequent processing element. However every processing element is processing just a single data stream at a time. Consequently, for managing multiple instruction streams in addition of single data stream, multiple processing elements and multiple control units are organised in this categorization. All processing elements are interacting with the common mutual memory for the organisation of single data stream as displayed in Figure. The simply known illustration of a computer capable of MISD function is the C.mmp made by Carnegie-Mellon University.
This kind of computer organisation is represented as:
Is > 1
Ds = 1
Figure: MISD Organisation
This categorization isn't popular in commercial machines as model of single data streams implementing on multiple processors is hardly ever applied. However for the particular applications, MISD organisation can be extremely helpful. E.g. Real time computers should be fault tolerant where various processors execute the similar data for generating the redundant data. This is also termed as N- version programming. All these redundant data are compared as results that must be same; or else faulty entity is replaced. So MISD machines can be applied to fault tolerant real time computers.
Hardware that calculates CRC (Cyclic Redundancy Check) uses: Hardware which computes CRC utilizes shift register and Xor unit.
Micro-instructions are stored in control memory. Address register for control memory comprises the address of subsequent instruction which is to be read. Control memory Buffer Regi
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