Explain high level data link control, Computer Engineering

Assignment Help:

Explain High Level Data Link Control.

HDLC - it is High Level Data Link Control:

Protocol Overall explanation:

Layer 2 of the OSI model is the data link layer. One of the most common layers 2 protocols is the HDLC protocol. The fundamental framing structure of the HDLC protocol is demonstrated below:

HDLC uses zero deletion/insertion process (commonly termed as bit stuffing) to make sure that the bit pattern of the delimiter flag does not arise in the fields among flags. The HDLC frame is synchronous and hence relies on the physical layer to give method of clocking and synchronizing the reception and transmission of frames. The HDLC protocol is defined through ISO for utilization on both point-to-point and multipoint (multidrop) data links. This supports full duplex transparent-mode operation and is at this time extensively used in multipoint and computer both networks.

High Level Data Link Control has three operational modes as:

a) Normal Response Mode (NRM)

b) Asynchronous Response Mode (ARM)

c) Asynchronous Balanced Mode (ABM)


Related Discussions:- Explain high level data link control

Resolution method, Resolution Method: For a minor miracle occurred in ...

Resolution Method: For a minor miracle occurred in 1965 where Alan Robinson published his resolution method as uses a method to generalised version of the resolution rule of i

Propositional inference rules - artificial intelligence, Propositional Infe...

Propositional Inference Rules -Artificial intelligence : Equivalence rules are specifically useful because of the vice-versa aspect,that means we can discover forwards andbackw

Microprocessor MIPS Full Adder and Divider with overflow, I need to write a...

I need to write a 32 bit adder in MIPS without using the Add command and a divider as well.

Nand gate, The NAND gate. The NAND gate is equivalent to an AND gate fo...

The NAND gate. The NAND gate is equivalent to an AND gate followed by a NOT gate so that the output is 0 when all of the inputs are high, otherwise the output is 1. There may

Computer architecture by henessy and patterson, what is initial interval an...

what is initial interval and latency in a functional unit(fp) of a pipeline

Explain fundamental models of inter process communication, Explain the two ...

Explain the two fundamental models of inter process communication. Two kinds of message passing system are given as: (a) Direct Communication : Along with direct communicat

Explain wait for graph-resource request and allocation graph, Explain Wait ...

Explain Wait for graph (WFG) with Resource request and allocation graph (RRAG). WFG with RRAG: A graph G = (V,E) is termed as bipartite if V can be decomposed in two

Structure tensor, what is structure tensor?how we calculate for image pixel...

what is structure tensor?how we calculate for image pixel?

Explain about magnetic disk, Q. Explain about Magnetic Disk? A disk is ...

Q. Explain about Magnetic Disk? A disk is circular platter constructed of nonmagnetic material known as substrate, coated with a magnetisable material. This is used for storing

Authorization bypass, Authorization Bypass is a frighteningly easy process ...

Authorization Bypass is a frighteningly easy process which can be employed with poorly designed applications or content management frameworks. You know how it is... you run a small

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd