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Hierarchical paging method
Most modern computer systems maintain a large logical-address space. In this situation the page table itself turns into excessively large. To remedy this memory wastage we won't allocate the page table contiguously in main memory.
One way is to utilize two-level paging algorithm, in which page table is as well paged. A logical address is separated into a page number consisting of 20 bits and a page offset consisting of 12 bits. for the reason that we page the page table, the page number is additional divided into a 10-bit page number and a 10 bit page offset. At this point address translation works as of the outer page table inwards this scheme is called as forward-mapped page table.
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are ''ASIC'' embeded systems
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