Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. Explain Hardwired control organization?
In the hardwired organization control unit is designed as a combinational circuit. The control unit is applied by gates, flip-flops, decoder and other digital circuits. Hardwired control units can be optimised for fast operations. Block diagram of control unit is displayed in Figure below. Major inputs to circuit are instruction register, clock, and flags. Control unit uses the opcode of instruction stored in IR register to perform various actions for various instructions. The Cu logic has unique logic input for every opcode. It simplifies the control logic. This control line selection can be executed by a decoder.
A decoder will have n binary inputs and 2n binary outputs. Every one of these 2n different input patterns will trigger a single unique output line.
Clock part of the control unit issues a repetitive sequence of pulses for SS duration of micro-operation(s). These timing signals control the sequence of execution of instruction as well as determine what control signal requires to applied at what time for instruction execution.
Figure: Block Diagram of Control Unit Operation
how to connect a home network
Which the digital logic family has the lowest propagation delay time ? Ans. ECL is the digital logic family that has the lowest propagation delay time. In ECL lowest propagati
How many select lines will a 32:1 multiplexer will have ? Ans. 5 select lines will be required for 32 inputs, as 2 5 = 32.
Explain about the organisations use in EDI. Organisations, which are use Electronic Data Interchange. Extensive users of Electronic Data Interchange (EDI) include: BHS:
What are threaded binary trees? A Threaded Binary Tree is a binary tree in which each node that does not have a right child has a THREAD (in real sense, a link) to its INORDER
Q. Calculate Register Transfer Time? A clock isn't included explicitly in any statements discussed above. But it is presumed that all transfers take place during clock edge tra
Do you have an experience on ArcGIS ?
Memory Stack Stack could exist as a stand-alone unit or could be executed in a random-access memory attached to the CPU. The implementation of a stack in a CPU is done by assig
Q. How can this arithmetic processor be associated to the CPU? Two mechanisms are used for connecting arithmetic processor to CPU. If an arithmetic processor is treated a
Q. Explain about Instruction Register and Flags? The Instruction Register: It comprises the operation code (opcode) and addressing mode bits of the instruction. It assists in
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd