Handlers Classification

In 1977, Wolfgang Handler suggested a complex notation for representing the pipelining and parallelism of computers. Handler's categorization addresses the computer at three different levels:

• Arithmetic logic unit (ALU)
• Bit-level circuit (BLC)
• Processor control unit (PCU)

The Processor control unit (PCU) communicates to a CPU or a processor, the ALU communicates to a processing element or a functional unit and Bit-level Circuit (BLC) communicates to the logic circuit required to perform 1-bit operations in the ALU.

Handler's categorization uses the subsequent three pairs of integers to explain a computer: 

      Computer = (p * p', a * a', b * b')

Where p = number of PCUs

Where p'= number of PCUs which can be pipelined

Where a = number of ALUs controlled by every PCU 

Where a'= number of ALUs which can be pipelined 

Where b = number of bits in ALU or processing element (PE) word

Where b'= number of pipeline segments on all ALUs or in a single PE

The subsequent operators and rules are used to illustrate the relationship between varieties of elements of computer:

• The '*' operator is used to refer that units are pipelined or macro-pipelined with a stream of data flowing via all the units.
• The '+' operator is used to refer that units aren't pipelined however work on independent streams of data.
• The 'v' operator is used to refer that the computer hardware is able to work in a number of modes.
• The '~' symbol is used to refer a range of values for any one of the parameters.
• Peripheral processors are displayed before the main processor by means of another three pairs of integer but If the value of the second element of any pair is 1, it might omit for brevity.

Handler's categorization is best described by showing how the rules and operators are used to categorize various machines.  The CDC 6600 has a single main processor sustained by 10 I/O processors. One CU (Control Unit) coordinates one ALU with a 60 bit word length. The ALU has 10 functional units that can be formed into a pipeline. The 10 peripheral I/O processors can work in parallel with each other and with the CPU. Every I/O processor encloses one 12-bit ALU. The elucidation for the 10 I/O processors is: 

  CDC 6600I/O = (10, 1, 12) 

The elucidation for the main processor is: 

  CDC 6600main = (1, 1 * 10, 60)

The major processor and I/O processors may be regarded as forming a macro-pipeline thus the '*' operator is used to join the two structures: 

CDC 6600 = (I/O processors) * (central processor    = (10, 1, 12) * (1, 1 * 10, 60)

Texas Instrument's "Advanced Scientific Computer (ASC)" has one controller organizing four arithmetic units. Every arithmetic unit is an 8- phase pipeline with 64 bit words. Therefore we have

ASC = (1, 4, 64 * 8)

The Cray-1 is a 64 bit single processor computer whose ALU has twelve functional units; eight of them can be chained together to form a pipeline. Dissimilar functional units have from 1 to 14 sections that can too be pipelined. Handler's elucidation of the Cray-1 is: 

Cray-1 = (1, 12 * 8, 64 * (1 ~ 14))

Another illustration system is 'Carnegie-Mellon University's C.mmp multiprocessor.' This system was aimed to facilitate research into parallel computer architectures and therefore can be comprehensively reconfigured. The system comprises 16 PDP-11 "minicomputers" (which have a 16 bit word length) interconnected by a crossbar switching network. In general the C.mmp functions in MIMD mode for which the description is (16, 1, 16). It is also able to operate in SIMD mode, where all processors are coordinated by a single master controller. The SIMD mode explanation is (1, 16, 16). Lastly, the system can be reconfigured to operate in MISD mode. Here the processors are organized in a chain with single stream of data flowing via all of them. The MISD modes description is (1 * 16, 1, 16). The 'v' operator is used to unite descriptions of the similar piece of hardware function in differing modes. So, Handler's description for complete C.mmp is: 

  C.mmp = (16, 1, 16) v (1, 16, 16) v (1 * 16, 1, 16)

The '*' and '+' operators are used to unite various separate pieces of hardware. The 'v' operator is of a dissimilar form to the other two in which it is used to unite the different functioning modes of a single piece of hardware.

While Flynn's categorization is simple to use, Handler's classification is burdensome. The direct use of numbers in the nomenclature of Handler's categorizations makes it much more conceptual and therefore difficult. Handler's classification is extremely geared in the direction of description of chains and pipelines. As it is well able to explain the parallelism in a single processor, the diversity of parallelism in multiprocessor computers is not addressed well.