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Fixed Arithmetic pipelines
We take the illustration of multiplication of fixed numbers. Two fixed point numerals are added by ALU (Arithmetic and logic unit) using shift and add operations. This serial execution makes multiplication a slow process. If we look at the multiplication procedure carefully then we study that this is the procedure of adding the multiple copies of shifted multiplicands as displayed below:
Now we can recognize the subsequent phases for pipeline:
These phases have been implemented by means of CSA tree as displayed in Figure below.
Figure: Arithmetic pipeline for Multiplication of two 6-digit fixed numbers
In 32bit IP Addressing scheme all 1's represent? All 1's represent limited broadcast in 32 bit IP Addressing scheme.
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