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Efficiency
The effectiveness of pipeline can be measured the same as the ratio of busy time span to total time span counting the idle time. Let c be clock period of a pipeline the effectiveness/efficiency E can be referred as:
E = (n. m. c) / m. [m.c + (n-1).c] = n / (m + (n-1)
As n-> ∞, E becomes 1
Enumerate about the Decimal Arithmetic Unit The user of the computer input data in decimal numbers and receives output in the decimal form. But a CPU with ALU can perform arith
(a) Explian two limitations of dead-box analysis. (b) Describe why memory analysis is difficult. (c) With reference to the "Shadow Walker" rootkit, explain what is meant by
Give the circuit of a TTL NAND gate and explain its operation in brief. Ans: Operation of TTL NAND Gate: Fig.(d) Demonstrates a TTL NAND gate with a totem pole output.
Differentiate between static and dynamic memory? The static RAM is simpler to use and has shorter read and write cycles. One of the main applications of static RAM is in execut
Describe the three mapping techniques used in cache memories with suitable Example. The cache memory is a fast memory that is inserted among the larger slower main memory and t
Define deadlock. A process requests resources; if the resources are not available at that time, the method enters a wait state. Waiting processes might never again change state
Q. Sequential Execution of Instructions in RISC? Let's describe pipelining in RISC with an illustration program execution sample. Take the given program (R denotes register).
Q. Prove using Boolean Algebra 1. AB + AC + BC' = AC + BC' 2. (A+B+C) (A+B'+C') (A+B+C') (A+B'+C)=A 3. (A+B) (A'+B'+C) + AB = A+B 4. A'C + A'B + AB'C + BC = C + A'B
What are modes of operation of centralized SPC? In about all the present day electronic switching systems utilizing centralized control, only a two-processor configuration is
#questifind core radius for single mode operation at 850nm in SI fibre with n1=1.480 & n2=1.47 what is NAon..
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