Explain balanced wye-connected load, Electrical Engineering

Assignment Help:

Balanced Wye-Connected Load

Let us consider a three-phase, four-wire 208-V supply system connected to a balanced wye connected load with an impedance of 10 20° , as shown in Figure (a). We shall solve for the line currents and draw the corresponding phasor diagram.

Conventionally it is assumed that 208 V is the rms value of the line-to-line voltage of the supply system, and the phase sequence is positive, or A-B-C, unless mentioned otherwise. The magnitude of the line-to-neutral (or phase) voltages is given by 208/√3, or 120 V. Selecting the line currents returning through the neutral conductor, as shown in Figure, we have

1407_Balanced Wye-Connected Load.png

Note that ¯VBC has been chosen arbitrarily as the reference phasor, as in Figure (b). Assuming the direction of the neutral current toward the load as positive, we obtain

1532_Balanced Wye-Connected Load1.png

That is to say that the system neutral and the star point of the wye-connected load are at the same potential, even if they are not connected together electrically. It makes no difference whether they are interconnected or not.

Thus, for a balanced wye-connected load, the neutral current is always zero. The line currents and phase currents are equal inmagnitude, and the line currents are in phasewith the corresponding phase currents. The line-to-line voltages, in magnitude, are √3 times the phase voltages, and the phase voltages lag the corresponding line voltages by 30°.

The phasor diagram is drawn in Figure(b), from which it can be observed that the balanced line (or phase) currents lag the corresponding line-to-neutral voltages by the impedance

55_Balanced Wye-Connected Load2.png

angle (20° in our example). The load power factor is given by cos 20° for our problem, and it is said to be lagging in this case, as the impedance angle is positive and the phase current lags the corresponding phase voltage by that angle.

The problem can also be solved in a simpler way by making use of a single-line equivalent circuit, as shown in Figure(c),

303_Balanced Wye-Connected Load3.png

in which ¯ VL-N is chosen as the reference for convenience. The magnitude of the line current and the power factor angle are known; the negative sign associated with the angle indicates that the power factor is lagging. By knowing that the line (or phase) currents ¯IA, ¯IB, ¯IC lag their respective voltages ¯VAN, ¯VBN, and ¯VCN by 20°, the phase angles of various voltages and currents, if desired, can be obtained with respect to any chosen reference, such as ¯VBC.


Related Discussions:- Explain balanced wye-connected load

Programming languages - introduction to microprocessors , Programming langu...

Programming languages As we  have seen  the evolution of computer  hardware  similarly  programming  languages also  have their  history  of development from  machine  language

Matlab, design analog normalised low pass filter by using matlab routine ch...

design analog normalised low pass filter by using matlab routine cheb1ap

What is permeability of magnetic materials, Q. What is permeability of magn...

Q. What is permeability of magnetic material? For magnetic material media, the magnetic flux density B, expressed in tesla (T) or Wb/m 2 , and the field intensity H, expressed

Indicate the condition of the overflow and carry bits, Q. Do the following ...

Q. Do the following operations with 8 bit bytes, and indicate the condition of the overflow and carry bits. a) 10111011 + 00000011 b) 11101101 + 11111001 c) 11011011 + 110

Explain 8259 pin diagram, Explain 8259 Pin Diagram. The 8259A adds 8 ve...

Explain 8259 Pin Diagram. The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. It can be expanded to 64 interrupt requests by using one master 8259A and

Explain cwd instructions in 8086 family, Explain CWD instructions in 8086...

Explain CWD instructions in 8086 family with example and their effect on flag. Convert signed word to signed double word: CWD instruction enlarges the sign bit of a word int

Cro, why is delay line used in vertical deflection on systems of CRO?

why is delay line used in vertical deflection on systems of CRO?

Right-handed coordinate system, The vectors we will use we be refered to ri...

The vectors we will use we be refered to right-handed Cartesian axes. Right handed means that the x,y,z axes are oriented in a particular way (which you must know). See diagrams

Illustrate in detail b-spline and cubic bezier surfaces, Define ruled surfa...

Define ruled surface and surface of revolution. Illustrate in detail B-spline and cubic Bezier surfaces with their important properties.

Auto transformer, winding turns of 415v step down transformer on 50%, 60% &...

winding turns of 415v step down transformer on 50%, 60% & 80% tapping

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd