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Question:
(a) Explain the issue associated with vertices when the scan line scan line polygon fill algorithm is being applied?
(b) Explain the logic of shortening edges to avoid problems associated with vertices for scan line polygon fill algorithm?
(c) By making use of appropriate examples, briefly explain the following anti-aliasing techniques:
a. Super-sampling b. Area sampling c. Pixel phasing
(d) When dealing with CIE chromaticity, explain how "shade" and "tint" effects might be produced to an original colour?
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A logic gate drives a load, which has a resistance of 1 kÙ and a capacitance of 20 pF. The printed circuit track connecting the gate to its load has an 40 pF capacitance to ground.
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