Q. Explain about Programmable Logic Array?

Until now individual gates are considered as fundamental building blocks from that different logic functions can be derived. With the advancement of technology integration achieved by integrated circuit technology has raised resulting in production of one to 10 gates on a single chip (in small scale integration). The gate level designs are created at gate level only however  if design is to be done employing these SSI chips design consideration required to be changed as some of such SSI chips may be used for creating a logic circuit. With VLSI and MSI we can put still more gates on a chip and can make gate interconnections on a chip also. This connection and integration brings benefits of reduced cost and size as well as increased speed. However main drawback faced in these kinds of VLSI & MSI chip is that for every logic function layout of gate and interconnection requires to be designed. Cost involved in making these custom designs is quite high. So came the concept of Programmable Logic Array which is a general purpose chip that can be readily accepted for any particular purpose.

PLA are designed for SOP form of Boolean function and comprises regular arrangements of AND, NOT and OR gate on chip. Every input to chip is passed through a NOT gate so input and its complement are available to every AND gate. Output of every AND gate is made available for every OR gate and output of every OR gate is considered as chip output. By making suitable connections any logic function can be realized in these Programmable Logic Arrays. 

Figure: Programmable Logic Array

The figure (a) presents a PLA of 3 inputs and 2 outputs. Please consider connectivity points, all these points can be linked if desired. Figure (b) presents an implementation of logic function:

O₀ = I₀. I₁. I₂ + I¯₀. I¯₁. I¯₂ and O₁ = I¯₀. I¯₁. I¯₂ + I¯₀. I¯₁ through PLA.