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Q. Explain about Mainframes computer?
Mainframes, capable of executing in excess of 53 MIPS, are high-performance, general- purpose computers supporting very large databases, ranging in price from one to ten million dollars. These are used by many universities, large businesses, and government agencies, and are supplied mainly by IBM. Examples include IBM 360, CDC 7600 of Control Data Corporation, and Texas Instrument Advanced Scientific Computer (TI-ASC).
Associativity of Connectives : Here brackets are very important in order to tell us where to perform calculations in arithmetic and logic. By using these brackets we evaluate
Address symbol table is generated by the (A) memory management software. (B) assembler. (C) match logic of associative memory. (D) generated by operating system
Q. What is Master Clock Signal in Control Unit? The Master Clock Signal: This signal causes micro-operations to be executed in a square. In a single clock cycle either a single
Continuous or Discrete - artificial intelligence: The behaviour of the coming data in from the environment will change how the agent should be programming. In particular, the
MIPS - computer architecture: The MIPS ISA, so far 3 instruction formats Fixed 32-bit instruction 3-operand, load-store architecture 32 general-purpose register
Distinguish between ROM, PROM, EPROM, EEPROM. Ans: ROM: It also called Read Only Memory is a Permanent Memory. The data is permanently stored and cannot be changed in Perm
Assignment 3: Naïve Bayes algorithm for text classification. First part: In this assignment, we will redo the task of classifying documents (assignment 2) using the same R
What is the use of boot block? For a computer to start running when powered up or rebooted it needs to have an initial program to run. This bootstrap program tends to be simple
Internal Path length It is described as the number of node traversed while moving by one particular node to any other node in the tree.
Given: • A sequence of n arrival times t0, t1, ..., tn-1, • a library of mlogically equivalent gates {(d0, c0), (d1, c1), ..., (dm-1,cm-1)} where d is delay and c is cost • a
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