Eliminating data hazards - computer architecture, Computer Engineering

Assignment Help:

Eliminating data hazards:

Forwarding

NOTE: In the following instance, computed values are in bold, whereas Register numbers are not.

Forwarding involves adding output data into a previous stage of the pipeline. For example, let's assume we desire to write the value 3 to register 1, (which already contains a six), and then add 7 to register 1 and hold the result in register 2, for instance

Instruction 0: Register 1 = 6

Instruction 1: Register 1 = 3

Instruction 2: Register 2 = Register 1 + 7 = 10

Following execution, register 2 would contain the value 10. Though, if Instruction 1 (write 3 to register 1) does not fully exit the pipeline before Instruction 2 begins execution, it means that Register 1 does not contain the value 3 when Instruction 2 performs its addition operation. In such type of event, Instruction 2 adds 7 to the old value of register 1 (6), and so register 2 would contain 13 instead for example Instruction 0: Register 1 = 6

Instruction 1: Register 1 = 3

Instruction 2: Register 2 = Register 1 + 7 = 13

This error takes place because before Instruction 1 has committed/stored Instruction 2 reads1 Register the result of its write operation to Register 1. Thus when Instruction 2 is reading the contents of Register 1, register 1 still contains 6, not 3.

Forwarding (described below) helps right such errors by depending on the fact that the output of Instruction 1 (which is 3) may be utilized by subsequent instructions before the value 3 is committed to/stored in Register 1.

Forwarding is implemented by putting back the output of an instruction into the previous stage(s) of the pipeline as soon as the output of that instruction is available.  Forwarding applied to our instance means that we do not wait to commit/store the output of Instruction 1 in Register 1 (in this instance, the output is 3) before making that output accessible to the subsequent instruction (in this particular case, Instruction 2). The effect is that Instruction 2 uses the right (the more recent) value of Register

1: the commit/store was made instantly and not pipelined.

With forwarding enabled, the ID/EX[clarification needed] stage of the pipeline now has 2 inputs: the value read from the register mention (in this instance, the value 6 from Register 1), and the new value of Register 1 (in this instance, this value is 3) which is sent from the next stage (EX/MEM)[clarification needed]. Additional control logic is utilized to determine which input to use.

813_Eliminating data hazards.png


Related Discussions:- Eliminating data hazards - computer architecture

Determine the nand gate, If  the input to T-flipflop is 100 Hz signal, the ...

If  the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is ? Ans. The  final  output  of  the  three  T-flip-flops in cascade is 12

There no polymorphic-type response, Why is there no polymorphic-type respon...

Why is there no polymorphic-type response from a create() or find() method? Ans) The EJB Specification forbids this behavior, and the weblogic.ejbc compiler checks for this beha

State about the computer memories, Computer Memories Computer memories...

Computer Memories Computer memories are either external or internal. Internal memories are either RAM (random access memory) or ROM (read only memory). External memories can t

How to clear a datagrid on a button click, How to clear a datagrid on a but...

How to clear a datagrid on a button click? You require to Clear the DataSource of the dataGrid. So try this: dataSet1.Clear(); dataGrid1.DataSource = dataSet1.TableNam

Illustrate fdma and tdma concepts., Mobile Computing 1. What is Wireles...

Mobile Computing 1. What is Wireless Protocol Requirements and also explain in brief medium access control protocol. 2. Illustrate FDMA and TDMA concepts. 3. What are the

What is sdram, Synchronous dynamic random access memory (SDRAM) is dynamic ...

Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is initialized with the system bus. Classic DRAM has an asynchronous interface, which m

Recursion, Ask qurecurrion for short noteestion

Ask qurecurrion for short noteestion

Why should i use cgi, CGI is significant whenever you require to retain sta...

CGI is significant whenever you require to retain state information about a user, or run an application which communicates with the server. Things like guestbook's, Chat clients, d

Analysis of sort bitonic, Analysis of Sort_Bitonic(X) The bitonic sorti...

Analysis of Sort_Bitonic(X) The bitonic sorting network needs log n number of phases for performing task of sorting the numbers. The first n-1 phases of circuit can sort two n/

Explain sequential sharing, Explain Sequential Sharing In this sharing ...

Explain Sequential Sharing In this sharing method, a file can be shared by just one program at a time, i.e. file accesses by P1 and P2 are spaced out over time. A lock field ca

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd