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Q. Two balanced, wye-connected, three-phase loads are in parallel across a balanced, three - phase 60- Hz, 208-Vsupply. The first load takes 12 kWat 0.6 power factor lagging, and the second load takes 15 kVA at 0.8 power factor lagging.
(a) Draw the power triangle for each load and for the combination.
(b) What is the total kVA supplied?
(c) Find the supply power factor, and specify whether lagging or leading.
(d) Compute the magnitude of the current drawn by each load and drawn from the supply.
(e) If wye-connected capacitors are placed in parallel with the two loads in order to improve the supply power factor, determine the value of capacitance in farads in each phase needed to bring the overall power factor to unity.
Q. (a) Draw the logic diagram of the enabled D latch using only NAND gates. (b) Complete the timing diagram of Figure (a) of theDlatchwhose block diagram and truth table are giv
Q. If the line of Problem 15.1.3 is made of copper whose resistivity ρ = 1.72×10 -8 ·m, determine the maximum length that can be used if losses are not to exceed 3 dB when f = 3
can i use steplaizer with capisetor step up valtage
Latch A 8 bit latch comprises of transparent latch D flip flop. It is commonly used to interface output device with microprocessor. A typical example of such 8 bit latc
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