Draw the logic diagram of 4-bit odd parity checkers, Computer Engineering

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Draw the logic diagram of 4-bit odd parity checkers using EX-NOR gates and explain its operation with the help of Truth table.

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4 bit odd parity checker by using XNOR circuit:-The purpose of parity checker, in which the additional bit is termed as parity. This can be either odd or even. The given below circuit will provide the 4 bit parity checker circuit.

2066_ogic diagram of 4-bit odd parity checker using EX-NOR gates.png

Logic diagram of 4-bit odd parity checker using EX-NOR gates

Parity checker networks are logic circuits along with exclusive – OR functions. Exclusive OR operation of parity bit is a scheme for finding errors throughout transmission of binary information. This is a more bit transmitted and after that checked at the receiving end for errors.

In this 4 bit odd parity checker, the three bits X,Y,Z represent the message and `P` is the parity bit. For odd parity bit `P` is produced, in order to make the total number of 1`s odd (containing P). The 3-bit message and the parity bit are transmitting to their destination; then they are applied to a parity checker circuit. An error happens throughout transmission if the parity of the four bits acquired is even, because binary information transmitted was initially odd. The output “C” of the parity checker must be “1”while an error happens that is when the number of 1’s in the four inputs is even.

750_4-bit odd parity checker.png

4-bit odd parity checker

Truth Table

                     Four bits received                                                                        Parity error check

x

y

 

z

 

P

 

C

0

0

 

0

 

0

 

------------- 1

0

0

 

0

 

1

 

------------- 0

0

0

 

1

 

0

 

------------- 0

0

0

 

1

 

1

 

------------- 1

0

1

 

0

 

0

 

------------- 0

0

1

 

0

 

1

 

------------- 1

0

1

 

1

 

0

 

------------- 1

0

1

 

1

 

1

 

------------- 0

1

0

 

0

 

0

 

------------- 0

1

0

 

0

 

1

 

------------- 1

1

0

 

1

 

0

 

------------- 1

1

0

 

1

 

1

 

------------- 0

1

1

 

0

 

0

 

------------- 1

1

1

 

0

 

1

 

------------- 0

1

1

 

1

 

0

 

------------- 0

1

1

 

1

 

1

 

------------- 1

 


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