Draw the circuit diagram of a Master-Slave J-K flip-flop, Computer Engineering

Assignment Help:

Draw the circuit diagram of a Master-slave J-K flip-flop using NAND gates. What is race around condition? How is it eliminated in a Master-slave J-K flip-flop?

Ans.

Using NAND Gates logic Diagram of Master-Slave J-K Flip-Flop:  Fig.(a) demonstrates the logic diagram of Master-Slave J-K Flip-Flop by using NAND gates.

1795_Draw the circuit diagram of a Master-slave J-K flip-flop.png

Fig.7(a) Logic Diagram of Master-Slave J-K FLIP-FLOP

The Race-around Condition: The difficulty of both inputs 1that means S = R = I being not permitted in an S-R Flip-Flop is removed in a J-K Flip-Flop through using the feedback connection from outputs to the inputs of the gates. There is into R-S Flip-Flop, the inputs do not change throughout the clock pulse (CK = 1), that is not true in J-K Flip-Flop due to the feedback connections. Notice that the inputs are J = K = 1 and Q = 0 and a pulse as demonstrated in Fig.(b) is applied to the clock input. After some time interval ?t equal to the propagation delay throughout two NAND gates in series, the output will be to Q = 1.

Now we contain J = K = 1 and Q = 1 and after other time interval of ?t the output will be back to Q = O. Therefore, for the duration tp of the clock pulse, the output will oscillate back and forth among 0 and 1. At the ending of the clock pulse, the value of Q is indefinite. This situation is termed to as the race-around conditions. So the race-around condition can be ignored if tp < ?t < T. Though, this may be not easy to satisfy this inequality due to very small propagation delays in ICs. A further practical method of overcoming such difficulty is the utilization of the master-slave (M-S) configuration.

223_Draw the circuit diagram of a Master-slave J-K flip-flop1.png

Fig. (b) a Clock Pulse

A master-slave J-K Flip-Flop is a cascade of two S-R Flip-Flops along with feedback from the outputs of the second to the inputs to the first as exemplified in Fig.(a). Positive (+ CLK) clock pulses are applied to the first Flip-Flop and the clock pulses are inverted before such are applied to the second Flip-Flop. While CK=1, the first Flip-Flop is enabled and the outputs QM and Q‾M act in response to inputs of theses i.e. J and K as per the Table. Now, the second Flip-Flop is inhibited since its clock is LOW (539_a Clock Pulse.png= 0). While CK goes LOW (539_a Clock Pulse.png= 1), the first Flip-Flop is reserved and the second Flip-Flop is enabled, since now its clock is HIGH (539_a Clock Pulse.png= 1). Thus, the outputs Q and Q‾ follow the outputs QM and Q‾M respectively as in second and third rows of Table. Because the second Flip-Flop simply follows the first one, it is referred to as the Slave and the first one as the Master. Therefore, this configuration is termed to as Master-Slave Flip-Flop. In such circuit, the inputs to the gates G3M and G4M don't change throughout the clock pulse; therefore the Race-around condition does not be present. The state of the Master-Slave Flip-Flop changes on the negative transition (trailing ending).

373_Truth Table of JK Master-Slave Flip-Flop.png

Table 7.1 Truth Table of JK Master-Slave Flip-Flop

 


Related Discussions:- Draw the circuit diagram of a Master-Slave J-K flip-flop

Microprocessor, illustration of Z80 instruction set Computer

illustration of Z80 instruction set Computer

Explain vector processing issues in pipelining, Vector Processing   A...

Vector Processing   A vector is an ordered set of similar type of scalar data items. The scalar tem may be a logical value, an integer or a floating point number. Vector proce

Importance of artificial intelligence, Businesses are interested in AI bec...

Businesses are interested in AI because of the characteristics it offers that no other systems type offers. That is AI ability to: a. Preserve Intelligence and Knowledge: C

Explain protection mechanism, Explain Protection mechanism. Protection...

Explain Protection mechanism. Protection mechanism: The subsequent mechanisms are commonly utilized for protecting files having programs and data. (a) Access controls list

Extract data from tables without using the event ''get'', Is it possible to...

Is it possible to extract data from tables without using the event 'GET' in the report with an appropriate LDB. False.   You can extract data from tables using Select stateme

Explain isdn addressing with a example, Explain ISDN Addressing with a exam...

Explain ISDN Addressing with a example. A sub address, though a part of the ISDN address, is not seems as an integral part of the numbering scheme. Sub-address is carried in a

Call the user methods by creating the object, Make a class library and desc...

Make a class library and describe class 'User'. In User class describe the public, protected and Friend functions. Make a console application andadd a reference to this library and

Time complexity in the worst case, Speicified the following piece of code: ...

Speicified the following piece of code: int i = 1; int j = 4; while (i     {      if (i%3 == 0) i+=3;      else i+=4;        if (j%2 == 0) j*=4;      els

Explain the while loop in c, Explain The while loop in C The while loop...

Explain The while loop in C The while loop keeps repeating an action until an associated test returns false. This is useful where the programmer does not know in advance how ma

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd