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Shared Memory
Shared Memory refers to memory component of a computer system in which the memory can accessed directly by any of the processors in the system.
Distributed Memory
Refers to the 'Network based memory' in which there isn't any common address space for several memory modules including the memory system of (networked) system. Normally, a processor or group of processors have a memory module associated with it, not dependent on the memory modules associated with other processors or group of processors.
What is an imperative statement? Ans. Shows an action to be performed throughout execution of assembled program is an imperative statement.
Calculate the maximum access time that can be permitted for the data and control memories in a TSI switch with a single input and single output trunk multiplexing 2500 channels. Al
Explain about the Voice recognition system These voice recognition systems recognise spoken words e.g. for disabled people who can't use keyboards where they speak commands rat
A model for parallel programming is an abstraction and is machine architecture independent. A model can be executed on several hardware and memory architectures. There are various
END DIRECTIVE: ENDS directive ends a segment and ENDP directive ends a procedure and END directive ends whole program which appears as last statement. ASSUME Directive: An .
If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is ? Ans. The final output of the three T-flip-flops in cascade is 12.5 H
Q. Calculate Print Speed of printers? Speed at which a printer prints is generally an important issue. Though the printer has to take a certain time to print. Printing time ris
how to prove the partial order R is a total order in discrete mathmetics and structures by topological sorting method in c programming
Example of circuit switching and S&F (Stored and Forward) switching is (A) Telephone and Post of Telegraph (B) Video Signal Post or Telegraph (C) Digital Signal P
The Transmission-Gate input is linked to the D_LATCH data input (D), the control input to the Transmission-Gate is linked to the D_LATCH enable input (EN) and the Transmission-Gate
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