Different models of computation-parallel algorithms, Computer Networking

Assignment Help:

There are various computational models for representing the parallel computers. In this part, we discuss various models. These models would give a platform for the designing as well as the analysis of the parallel algorithms.

Combinational Circuits

Combinational Circuit is one of the forms for parallel computers. In interconnection networks, many processors communicate with each other directly and do not need a shared memory in between. Mostly, combinational circuit (cc) is a connected arrangement of logic gates with a set of m input lines and a set of n output lines as given in Figure. The combinational circuits are mostly made up of various interconnected components arranged in the form called as stages as given in Figure.

587_Combinational circuit.png

                                                                          Combinational circuit

2413_Detailed combinational circuit.png

Detailed combinational circuit

It might be noted here that there is no feedback control employed in combinational circuits. There are a small number of terminologies followed in the context of combinational circuits such as fan in and fan out. Fan in indicates the number of input lines attached to each device and fan out indicates the number of output lines. In Figure , the fan in is 3 and fan out is also 3. The following parameters are used for analyzing a combinational circuit:

1)  Depth: It means that the total number of phases used in the combinational circuit starting from the input lines to the output lines. For example, in the depth are 4, as there are four different phases attached to a interconnection network. The other form of interpretation of depth can be that it represents the worst case time complexity of resolving a problem as input is given at the initial input lines and data is transmitted between various phases through the interconnection network and at the end reaches the output lines.

2) Width: It represents the total number of devices attached for a particular phase. For example in Figure, there are 4 components linked to the interconnection network. It means that the width is 4.

3)  Size: It represents the total count of devices used in the complete combinational circuit. For example, in Figure , the size of combinational circuit is 16 i.e. (width * depth).


Related Discussions:- Different models of computation-parallel algorithms

What is the full form of FDM and TDM, What is the full form of FDM and TDM ...

What is the full form of FDM and TDM It is both. Each of the 100 channels is possess its own frequency band (FDM), and on every channel two logical streams are intermixed by th

Synchronous tdm and statistical tdm, Difference between synchronous tdm and...

Difference between synchronous tdm and statistical tdm

Example on multiplicative decrease, Q. Example on Multiplicative Decrease? ...

Q. Example on Multiplicative Decrease? w = 1 for (each new ACK received) w = w+1 until (loss detected or w >= ssthresh) Not so slow - Exponential increase

Html, write a html program segment that contains hypertext links from one d...

write a html program segment that contains hypertext links from one document to anothersk question #Minimum 100 words accepted#

Tcp segment structure - transport layer, TCP Segment Structure Figure ...

TCP Segment Structure Figure shows the format of the TCP segment. The  header consists  of a 20 bytes  fixed  part  plus a variable size  options fields. The description  o

Explain the term ftp- file transfer protocol, Explain the term FTP: File T...

Explain the term FTP: File Transfer Protocol A very common method of moving files between two Internet sites. FTP is a special way to log in to another Internet site for pur

asymmetric multiprocessing, Describe what is meant by Asymmetric Multiproc...

Describe what is meant by Asymmetric Multiprocessing (AMP)? Ans) It imposses hierarchy and a division of labour between processors. Only one designated processor, the master, co

Layer responsible for putting 1s and 0s into a logical group, Name the laye...

Name the layer responsible for putting 1s and 0s into a logical group? Ans) Frames are broken down into 1s and 0s and placed onto the physical medium by the Data Lin layer.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd