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You have two counters counting up to 16, built through negedge DFF, First circuit is synchronous and second is "ripple" as cascading, which circuit has a less propagation delay? Why?
The synchronous counter will have lesser delay like the input to each flop is readily obtainable before the clock edge. While the cascade counter will obtain long time as the output of one flop is utilized as clock to the other. Therefore the delay will be propagating. For example, 16 state counter = 4 bit counter = 4 Flip flops Let 10ns be the delay of every flop.
The worst case delay of ripple counter i.e., = 10 * 4 = 40ns. The delay of synchronous counter = 10ns only. There is Delay of 1 flop.
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