Determine about the Verilog Task

- Tasks are capable of enabling a function as well as enabling other versions of a Task.

- Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time.

- Tasks are allowed to contain any of these statements.

- A task is allowed to use zero or more arguments which are of type output, input or inout.

- A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements.

- Tasks are not synthesisable.

- Disable statements can be used.