Design combinational-sequential electronic logic gate, Computer Engineering

Assignment Help:

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package)

Car wash concept with the following steps in a Combinational Logic Diagram:

1.    Start Rinse   

2.    Stop Rinse, Start Soap

3.    Start Brush

4.    Stop Soap, Stop Brush

5.    Start rinse

6.    Stop rinse, Start Dry

7.    Stop Dry

A corresponding LED will light-up when the step is reached on during the car wash sequence/run.  Each LED will be on for 5 seconds.  For steps 2, 4, and 6, those LEDs will light for 8 seconds.

Requirements:  Design Combinational/sequential electronic logic diagram with integrated Circuit items depicted an automated Car Wash process.  All of the integrated circuits used thus far in the course have been 74LS00s and 74000s series.

From the diagram I will actually construct the project on a Pencil Box Logic Designer which has an experimental breadboard. Items used in/on the diagram will include some of the following ICs that can be placed on breadboard:

Logic Gates:

AND gate

Exclusive-OR (XOR) gate

Inverter gate

NAND gate

NOR gate

OR gate

TIMER

Half-Adder

Full-Adder

Comparators

Binary Decoders

Binary-to-Decimal Decoders

Multiplexer (MUX)

Demultiplexer (DEMUX)

Latch

S-R Latch

Gated S-R Latch

D Latch

FLIP-FLOPS

D flip-flop

J-K flip-flop

One shot

Counters & Counter logic operations

Shift Registers

Serial In/Serial Out

Serial In/Parallel Out

Note: Some of the items on the list are combinations of several ICs.  Example: Instead of using XOR gate for logic functions on the diagrams, it can also be a combination of 2 x Inverter Gates, 2 x AND Gates, & 1 x OR Gate.

The PencilBox Logic Designer which I'm using has Logic Indicators (8 x LED), CLOCK, Logic 8 x Switches, 2 x PULSERS push buttons.

The last diagram I completed was a 4-Bit Counter.  See below:

492_4 bit binary counter.png


Related Discussions:- Design combinational-sequential electronic logic gate

Data parallel model - parallel programming model, In the data parallel mode...

In the data parallel model, many of the parallel work focus on performing operations on a data set. The data set is usually organized into a common structure, such as an array or a

Produce an analysis model of the proposed system, Question: Read the fo...

Question: Read the following case study and answer the questions based on it. The local airline company needs to develop a system for controlling air traffic at the airport

Node at the highest level in the structure, Node at the highest level in th...

Node at the highest level in the structure is known as?? Root.

What is a spool request, What is a Spool request? Spool requests are f...

What is a Spool request? Spool requests are formed during dialog or background processing and placed in the spool database with information about the printer and print format.

Signaling pvm process, Q. Signaling PVM process? int pvm_sendsig( ...

Q. Signaling PVM process? int pvm_sendsig( int tid, int signum ) Transmits a signal to other PVM process. tid is task identifier of PVM process to receive signal.

Pci bus transactions - computer architecture, PCI bus transactions: PC...

PCI bus transactions: PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phas

Android mobile application, Students are needed to work in group of 3 and m...

Students are needed to work in group of 3 and make an Android mobile application falling under the following categories: Multimedia o    Eg: Camera app, mp3 player, ga

The information on the current screen, How do you find the information on t...

How do you find the information on the current screen? The information on the present screen can be found by SYSTEM ? STATUS command from any menu.

Explain the probability of availability of free lines, How does one arrive ...

How does one arrive at the probability of availability of free lines during the busy hour? One can arrive at the possibility of free lines throughout busy hour using the delay

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd