Design combinational-sequential electronic logic gate, Computer Engineering

Assignment Help:

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package)

Car wash concept with the following steps in a Combinational Logic Diagram:

1.    Start Rinse   

2.    Stop Rinse, Start Soap

3.    Start Brush

4.    Stop Soap, Stop Brush

5.    Start rinse

6.    Stop rinse, Start Dry

7.    Stop Dry

A corresponding LED will light-up when the step is reached on during the car wash sequence/run.  Each LED will be on for 5 seconds.  For steps 2, 4, and 6, those LEDs will light for 8 seconds.

Requirements:  Design Combinational/sequential electronic logic diagram with integrated Circuit items depicted an automated Car Wash process.  All of the integrated circuits used thus far in the course have been 74LS00s and 74000s series.

From the diagram I will actually construct the project on a Pencil Box Logic Designer which has an experimental breadboard. Items used in/on the diagram will include some of the following ICs that can be placed on breadboard:

Logic Gates:

AND gate

Exclusive-OR (XOR) gate

Inverter gate

NAND gate

NOR gate

OR gate

TIMER

Half-Adder

Full-Adder

Comparators

Binary Decoders

Binary-to-Decimal Decoders

Multiplexer (MUX)

Demultiplexer (DEMUX)

Latch

S-R Latch

Gated S-R Latch

D Latch

FLIP-FLOPS

D flip-flop

J-K flip-flop

One shot

Counters & Counter logic operations

Shift Registers

Serial In/Serial Out

Serial In/Parallel Out

Note: Some of the items on the list are combinations of several ICs.  Example: Instead of using XOR gate for logic functions on the diagrams, it can also be a combination of 2 x Inverter Gates, 2 x AND Gates, & 1 x OR Gate.

The PencilBox Logic Designer which I'm using has Logic Indicators (8 x LED), CLOCK, Logic 8 x Switches, 2 x PULSERS push buttons.

The last diagram I completed was a 4-Bit Counter.  See below:

492_4 bit binary counter.png


Related Discussions:- Design combinational-sequential electronic logic gate

Problem context and specification, Problem Context and Specification : ...

Problem Context and Specification : However the development of Inductive Logic Programming has been heavily formal in mathematical in nature it means the major people in the f

Explain about subsystem and object of object oriented, Explain about subsys...

Explain about subsystem and object of object oriented modeling A subsystem is a grouping of elements of that constitutes a specification of behaviour offered by other contained

Face recognition using java, how we get a perfect tutorial for face recogn...

how we get a perfect tutorial for face recognition using java

Microcomputer applications, Mr. Franco Forest owns a small lawn care busine...

Mr. Franco Forest owns a small lawn care business with three employees. He owns the lawn mowers, rakes, and weed whackers that are housed in a storage area at the back of his home.

Signaling - universal serial bus , Signaling - Universal Serial Bus: U...

Signaling - Universal Serial Bus: USB supports following signaling rates: o   A low speed rate of 1.5 Mbit/s is defined by USB 1.0. This is so much similar to "full speed"

Which approaches not require knowledge of the system state, Which approache...

Which approaches do not require knowledge of the system state? Ans. Deadlock detection, deadlock prevention and deadlock avoidance; none of the given require knowledge of the s

Which one logic gate can generate any logic function, A universal logic gat...

A universal logic gate is one, which can be used to generate any logic function.  Which one is a universal logic gate? Ans. NAND gate is a universal logic gate; it can generate

How blocking and non blocking statements get executed, How blocking and non...

How blocking and non blocking statements get executed? Execution of blocking assignments can be viewed just like a one-step process: 1. Evaluate RHS (right-hand side equatio

Define deadlock with resource request and allocation graph, Define Deadlock...

Define Deadlock with Resource request and allocation graph (RRAG) Deadlocks can be described through a directed bipartite graph termed as a RRAG that is Resource Request All

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd