Design combinational-sequential electronic logic gate, Computer Engineering

Assignment Help:

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package)

Car wash concept with the following steps in a Combinational Logic Diagram:

1.    Start Rinse   

2.    Stop Rinse, Start Soap

3.    Start Brush

4.    Stop Soap, Stop Brush

5.    Start rinse

6.    Stop rinse, Start Dry

7.    Stop Dry

A corresponding LED will light-up when the step is reached on during the car wash sequence/run.  Each LED will be on for 5 seconds.  For steps 2, 4, and 6, those LEDs will light for 8 seconds.

Requirements:  Design Combinational/sequential electronic logic diagram with integrated Circuit items depicted an automated Car Wash process.  All of the integrated circuits used thus far in the course have been 74LS00s and 74000s series.

From the diagram I will actually construct the project on a Pencil Box Logic Designer which has an experimental breadboard. Items used in/on the diagram will include some of the following ICs that can be placed on breadboard:

Logic Gates:

AND gate

Exclusive-OR (XOR) gate

Inverter gate

NAND gate

NOR gate

OR gate

TIMER

Half-Adder

Full-Adder

Comparators

Binary Decoders

Binary-to-Decimal Decoders

Multiplexer (MUX)

Demultiplexer (DEMUX)

Latch

S-R Latch

Gated S-R Latch

D Latch

FLIP-FLOPS

D flip-flop

J-K flip-flop

One shot

Counters & Counter logic operations

Shift Registers

Serial In/Serial Out

Serial In/Parallel Out

Note: Some of the items on the list are combinations of several ICs.  Example: Instead of using XOR gate for logic functions on the diagrams, it can also be a combination of 2 x Inverter Gates, 2 x AND Gates, & 1 x OR Gate.

The PencilBox Logic Designer which I'm using has Logic Indicators (8 x LED), CLOCK, Logic 8 x Switches, 2 x PULSERS push buttons.

The last diagram I completed was a 4-Bit Counter.  See below:

492_4 bit binary counter.png


Related Discussions:- Design combinational-sequential electronic logic gate

Towers of hanoi problem, The Towers of Hanoi Problem Towers of Hanoi pro...

The Towers of Hanoi Problem Towers of Hanoi problem is described. There are three pegs on which disks are "threaded" (there are holes in the disks to allow them to be placed on

Direct or random access of elements, Direct or random access of elements is...

Direct or random access of elements is not possible in:- In Linked list direct or random access of elements is not possible

State briefly about the register transfer, State briefly about the  Regist...

State briefly about the  Register Transfer A micro operation is a basic operation performed on information stored in one or more registers. The result of operation may replace

Computer network, how Hierarchical Routing implement in c or cpp

how Hierarchical Routing implement in c or cpp

Explain about iframe, Q. Explain about IFRAME? is an HTML 4.0 addition...

Q. Explain about IFRAME? is an HTML 4.0 addition to frames toolbox. Presently only MSIE supports . Unlike frames created employing and

Explain a schematic diagram of thousand line exchanges, Using a combination...

Using a combination of uniselectors and two motion selectors draw a schematic of thousand line exchanges. The schematic diagram for such an exchange is demonstrated in Fig. All

Define parsing, Define Parsing Parsing is the method of analyzing a te...

Define Parsing Parsing is the method of analyzing a text, made up of a sequence of tokens, to define its grammatical structure with respect to a given formal grammar. Parsing

A function declaration and function definition, Explain the difference betw...

Explain the difference between a function declaration and function definition.    Function declaration and Function definition:  A function declaration having the name of th

Evaluate - 48 - 23 by using the 2's complement method, Perform the - 48 - 2...

Perform the - 48 - 23 operations using the 2's complement method. Ans. - 48 - 23 = - 48 + (-23)     -48     =  1 1 0 1 0 0 0 0     -23     =  1 1 1 0 1 0 0 1       = -71

Address phase - computer architecture, Address phase: A PCI bus transa...

Address phase: A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd