Design combinational-sequential electronic logic gate, Computer Engineering

Assignment Help:

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package)

Car wash concept with the following steps in a Combinational Logic Diagram:

1.    Start Rinse   

2.    Stop Rinse, Start Soap

3.    Start Brush

4.    Stop Soap, Stop Brush

5.    Start rinse

6.    Stop rinse, Start Dry

7.    Stop Dry

A corresponding LED will light-up when the step is reached on during the car wash sequence/run.  Each LED will be on for 5 seconds.  For steps 2, 4, and 6, those LEDs will light for 8 seconds.

Requirements:  Design Combinational/sequential electronic logic diagram with integrated Circuit items depicted an automated Car Wash process.  All of the integrated circuits used thus far in the course have been 74LS00s and 74000s series.

From the diagram I will actually construct the project on a Pencil Box Logic Designer which has an experimental breadboard. Items used in/on the diagram will include some of the following ICs that can be placed on breadboard:

Logic Gates:

AND gate

Exclusive-OR (XOR) gate

Inverter gate

NAND gate

NOR gate

OR gate

TIMER

Half-Adder

Full-Adder

Comparators

Binary Decoders

Binary-to-Decimal Decoders

Multiplexer (MUX)

Demultiplexer (DEMUX)

Latch

S-R Latch

Gated S-R Latch

D Latch

FLIP-FLOPS

D flip-flop

J-K flip-flop

One shot

Counters & Counter logic operations

Shift Registers

Serial In/Serial Out

Serial In/Parallel Out

Note: Some of the items on the list are combinations of several ICs.  Example: Instead of using XOR gate for logic functions on the diagrams, it can also be a combination of 2 x Inverter Gates, 2 x AND Gates, & 1 x OR Gate.

The PencilBox Logic Designer which I'm using has Logic Indicators (8 x LED), CLOCK, Logic 8 x Switches, 2 x PULSERS push buttons.

The last diagram I completed was a 4-Bit Counter.  See below:

492_4 bit binary counter.png


Related Discussions:- Design combinational-sequential electronic logic gate

What do you mean by shared memory, Q. What do you mean by Shared Memory? ...

Q. What do you mean by Shared Memory? In shared memory scheme more focus is on controlling parallelism instead of data parallelism. In this model numerous processes run indepen

On what machines matlab should be run?, Matlab will run from sthelens, and ...

Matlab will run from sthelens, and only if sthelens is down, from cher, orsay or tiree. It runs on other machines too, but some of the other machines have older versions of the OS

Electrically erasable programmable read only memory- EEPROM, Electrically e...

Electrically erasable programmable read only memory (EEPROM) An EEPROM is a special type of PROM which can be erased by exposing it to an electrical charge. Like other kinds of

What is a piconet in a bluetooth context, Problem: (a) IEEE802.11 supp...

Problem: (a) IEEE802.11 supports two types of network architecture, describe these architectures with the support of diagrams detailing the network components. (b) The MAC

Explain the raster scan monitors, Explain the raster scan monitors The ...

Explain the raster scan monitors The refresh process must also be performed for raster scan monitors. Most television monitors are raster scan display devices : one scan-line a

Double negation, Double Negation : All parents are forever correcting ...

Double Negation : All parents are forever correcting their children for the find of double negatives,  there we have to be very alert with them in natural language like: "He d

Basic logic gates, Basic logic gates Introduce the basic logic gates i...

Basic logic gates Introduce the basic logic gates in terms of a) their function, b) their circuit symbol, c) their truth table and d) their equivalent in Boolean a

Jewel polishing, Byteland county is very famous for luminous jewels. Lumino...

Byteland county is very famous for luminous jewels. Luminous jewels are used in making beautiful necklaces. A necklace consists of various luminous jewels of particular colour. Nec

Sequential logic gates - sr flip flop, Sequential Logic Gates SR flip ...

Sequential Logic Gates SR flip flop                                                                                                                    1)

How debugger works internally, Whenever we compile with -g option, it will ...

Whenever we compile with -g option, it will make a symbol table, and according that table for every function and line it will call ptrace.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd