Describe target processor arrangements, Computer Engineering

Assignment Help:

Q. Describe target processor arrangements?

Having seen how to describe one or more target processor arrangements we need to initiate mechanisms for distributing data arrays over those arrangements. The DISTRIBUTE directive is used to distribute a data object on an abstract processor array.

The syntax of a DISTRIBUTE directive is:   

!HPF$ DISTRIBUTE  array_lists  [ONTO arrayp]

where array_list is the list of array to be distributed and arrayp is abstract processor array.

The ONTO specifier can be used to carry out a distribution across a specific processor array. If any processor array is not specified one is automatically chosen by compiler. 

HPF permits arrays to be distributed over the processors directly however it is frequently more suitable to go through intermediary of an explicit template. A template can be declared in much the similar way like processor arrangement.

!HPF$ TEMPLATE T(50, 50, 50)

Declares a 50 by 50 by 50 three-dimensional template known as T. Having declared it we are able to establish a relation amid some processor arrangement and a template by employing DISTRIBUTE directive. There are 3 ways in that a template can be distributed over Processors: Block, cyclic and *. 

(a) Block Distribution

Simple block distribution is specified by 

!HPF$ DISTRIBUTE T1(BLOCK) ONTO P1

Where T1 is a template and P1 is a processor arrangement.

In this case every processor gets a contiguous block of template elements. All processors obtain the similar sized block. The final processor can get lesser sized block.


Related Discussions:- Describe target processor arrangements

What is the role of certifying authority, What is the Role of Certifying Au...

What is the Role of Certifying Authority? A certificate authority is a body, that is either public or private, that seeks to fill the requirement for trusted third-party servic

user to enter the weight, A red and blue car were involved in a head-on co...

A red and blue car were involved in a head-on collision. The red car was at a standstill and the blue car was possibly  speeding. Eye witness video recorded suddenly following the

Explain 16-bit ROM array, Draw the logic diagram of 16-bit ROM Array and ex...

Draw the logic diagram of 16-bit ROM Array and explain its principle of operation. Ans: 16-bit ROM Array: A ROM that is read-only memory is an array of selectively closed

Determine about the microprocessor, Determine about the microprocessor ...

Determine about the microprocessor A microprocessor contains at the least CPU which was the case in 1970s and early 1980s. Today they include cache memories, bus interfaces, an

Explain the term granularity, Granularity In 'Parallel computing', Gran...

Granularity In 'Parallel computing', Granularity can be defined as a qualitative assess of the ratio of computation to communication. 1) Coarse Granularity - relatively hug

Coding advantages of casex or casez, Coding advantages of casex or casez ...

Coding advantages of casex or casez By using casex or casez has the following coding advantages: -  It reduces number of lines, especially if the number of bits had been m

What is block size of cache memory, Q. What is Block size of cache memory? ...

Q. What is Block size of cache memory? Block Size: Block size means unit of data (few memory words) exchanged between main and cache memory. As block size increases from very

Illustrate edge-triggered flip-flops, Q. Illustrate Edge-Triggered flip-flo...

Q. Illustrate Edge-Triggered flip-flops ? Edge-triggered flip-flop is used to synchronize state change at the time of a clock pulse transition in place of constant level. A num

Balanced trees and their operations, what is ment by avl tree n insertion n...

what is ment by avl tree n insertion n deletion ,2-3 tress insertion n deletion

Illustrate cache dram, Q. Illustrate Cache DRAM? Cache DRAM (CDRAM) wh...

Q. Illustrate Cache DRAM? Cache DRAM (CDRAM) which is developed by Mitsubishi integrates a tiny SRAM cache (16Kb) on a generic DRAM chip. SRAM on the CDRAM can be used in two

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd