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Q. Describe about Immediate Addressing mode?
When an operand is interpreted as an immediate value for example LOAD IMMEDIATE 7 it is actual value 7 which is put in CPU register. In this mode operand is the data in operand address field of instruction. Subsequently there is no address field at all and henceforth no extra memory accesses are needed for executing this instruction. Or we can say that in this addressing scheme the actual operand D is A the content of operand field: it implies that D = A. The effective address in this case isn't defined:
Figure: Immediate Addressing
Show Library and its types. Libraries constitute a simple meaning of gathering many object files together: 1. Static: during link editing Library code is integrated with t
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Differentiate between protection and security. Operating system contains a collection of objects, software or hardware. All objects have a unique name and can be accessed by
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Handshake control of data transfer during an input operation: . Handshake control of data transfer during an output operation o Interface to CPU and Memory o
Elucidate the purpose of GDTR. If the microprocessor sends linear address 00200000H to paging mechanism, which paging directory entry and which page table entry is accessed? GD
Compare a decoder and a demultiplexer with suitable block diagrams. Ans. Demultiplexer has similar circuit as decoder but here e is obtained as the particular input line, the
Q. Average data transfer rate in floppy? A floppy is about 0.64 mm thick and is available in diameters 5.25 inch and 3.5 inch. Data are arranged in form of tracks and sectors.
Vuser_init action haves procedures to login to a server.
Cache-Only Memory Access Model (COMA) As we have discussed previous, shared memory multiprocessor systems may use cache memories with each processor for deducting the execution
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