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Define the Edge-Triggered Flip-flops?
An edge-triggered flip-flop changes states either at the negative edge (falling edge) or at the positive edge (rising edge) of the clock pulse on the control input. The three basic kinds are introduced here: S-R, J-K and D.
The S-R, J-K and D inputs are called as synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called as asynchronous inputs as they are inputs that affect the state of the flip-flop independent of the clock. For a synchronous operation to work properly, these asynchronous inputs should both be kept LOW.
State the structure of Verilog code you follow? A good template for your Verilog file is shown below. // timescale directive tells the simulator the base units and precision
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