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Q. Define about Hyper-threading technology?
Hyper-threading technology enables a single microprocessor to behave as two separate threaded processors to operating system and application program which use it.
Hyper-threading requires software that has multiple threads and optimizes speed of execution. A threaded program executes rapidly on hyper threaded machine. Though it must be noted that not every program can be threaded.
The other architecture that has gained popularity over last decade is power PC family. These machines are called as Reduced set instruction computer (RISC) based technologies. RISC technologies are finding their application because of simplicity of Instructions. The IBM made an alliance with Apple and Motorola who has used Motorola 68000 chips in their Macintosh computer to make POWER PC architecture. A number of the processors in this family are:
Figure: Power PC Family
Implement the Y(A, B, C) = ∑(2,3,5,6) function using 4-to-1 multiplexer. Ans. Y(A,B,C)=∑(2,3,5,6) Here we take B,C as the select bits also A as input. To select the input we can
The first part of the address in electronic mailbox identifies? The first part of address in E-Mail identifies the user's mail box.
Write a program to mask bits D3D2D1D0 and to set bits D5D4 and to invert bits D7D6 of the AX register.
what are the questionnaries and observation of work site for banking system?
Illustrate the benefits of Functional model Functional model shows how values are computed. This model describes decisions or object structure without regard for sequencing. I
Q. Rank the list elements in terms of distance? Rank the list elements in terms of distance from each to last element in given linear linked list. A parallel algorithm for t
When designing a logic circuit with multipleoutputs it is usual to treat it as several circuitseach with one output. So for our example wewould design three circuits; one with outp
What is a Demultiplexer ? Ans. Demultiplexer has similar circuit as decoder but here E is obtained as the particular input line, the output lines are similar as decode
Design an OR to AND gates combinational network and NAND only n/w for the following Boolean expression: A'BC'D + ABC'D' + A'B'CD' + A'BCD'
duality
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