De morgan''s laws - artificial intelligence, Computer Engineering

Assignment Help:

De Morgan's Laws

Continuing with the relationship between  and , we can also use De Morgan's Law to rearrange sentences involving negation in conjunction with these connectives. Actually, there are 2 equivalences which taken as a pair are called De Morgan's Law:

¬(P Q) ≡ ¬P ∨¬Q

¬ (P ∨ Q) ≡ ¬P  ¬Q

These are essential rules and it is good spending some time thinking regarding why they are true.

Contraposition

The contraposition equivalence is following:

P -> Q ≡ ¬Q -> ¬P

At first, this can seem a little strange because it seem that we have said nothing in the first sentence regarding ¬Q, soin the second sentence how can we infer anything from it? However, imagine we know that P implies Q, and we saying that Q was false. In this case, if we were to imply that P was true because we know that P implies Q, we also know that Q is true. But Q was false .So we cannot possibly denote that P is true, which means that we ought to imply that P is false (because we are in propositional logic, so P might be either true or false). This argument shows that we may replace the first sentence by the second one, and it is left as aworkout to construct a similar argument for the vice-versa part of this equivalence.


Related Discussions:- De morgan''s laws - artificial intelligence

Arbitrary categorisation - learning decision trees, Arbitrary categorisatio...

Arbitrary categorisation - learning decision trees: Through visualising  a set of boxes with some balls in. There if all the balls were in a single box so this would be nicely

Design a sequential circuit with two flip-flop and one input, Design a coun...

Design a counter modulo 4 (sequential circuit with two flip-flops and one input U) which work like that: 1. When U=0, the state of the flip-flop does not change. 2. Whe

What is replacement policy in cache, Q.What is Replacement Policy in cache?...

Q.What is Replacement Policy in cache? When a new block has to be fetched in cache the other block may have to be replaced to make room for new block. Replacement policy determ

What is the difference between in two lines of verilog code, What is the di...

What is the difference between the following two lines of Verilog code? #5 a = b; a = #5 b; #5 a = b; Wait five time units before doing the action for "a = b;". Value assig

Bus master - computer architecture, Bus Master: In  computer system,  ...

Bus Master: In  computer system,  bus  mastering  is  a attribute  supported  by  various  bus  architectures  that  enables  a  device linked to the bus to initiate transacti

., advantages and disadvantages of a header node

advantages and disadvantages of a header node

Corresponding port numbers, A) Around how many entries are there in this fi...

A) Around how many entries are there in this file on your VM? B) Select and list names and corresponding port numbers for four well-liked services listed in this file?

Shared-memory programming model, Q. Shared-memory programming model? In...

Q. Shared-memory programming model? In shared-memory programming model tasks share a common address space that they read and write asynchronously. Several mechanisms like semap

Specifying optimisation criteria of describe function, Specifying Optimisat...

Specifying Optimisation Criteria Specify values to be minimized, maximized or optimized. You can understand it as way you normalize data in database. For instance, you should

Explain the memory transfer process, Q. Explain the Memory Transfer process...

Q. Explain the Memory Transfer process? Memory Transfer Transfer of information from memory to outside world which implies I/O Interface is known as a read operation. Tra

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd