Data packets - universal serial bus, Computer Engineering

Assignment Help:

Data packets:

A data packet consists of the PID which is followed a 16-bit CRC and by 0-1023 bytes of data payload (up to 1024 in high speed and at most 8 at low speed)

There are 2 basic data packets, DATA0 and DATA1. They have to always be preceded by an address token, and are typically followed by a handshake token from the receiver back to the transmitter. The 2 packet types provide the 1-bit sequence number needed by Stop-and-wait ARQ. If a USB host does not retain a response (such as an ACK) for data it has transmitted, it doesn't know if the data was retained or not; the data may have been lost in transit, or it may have been received but the handshake response was lost.

To solve this type of problem, the device keeps track of the type of DATA x packet it last accepted. If it retains another DATA x packet of the similar type, it is acknowledged but ignored as a case of duplicate. Only a DATA x packet of the opposite type is really received.

When a device is reset having a SETUP packet, it expects an 8-byte DATA0 packet next.

USB 2.0 added DATA2 and MDATA packet types as well. They are used just by high-speed devices doing high-bandwidth isochronous transfers which required transferring more than 1024 bytes per 125 µs "micro frame" (8192 kB/s),PRE "packet"

Low-speed components are supported with a special PID value, PRE. It marks the beginning of a low-speed packet, and it is used by hubs which usually do not send full-speed packets to low-speed devices. As all PID bytes include four 0 bits, they leave the bus in the FS(full speed)K state, which is the similar as the low-speed J state. It is followed by a deep pause during which hubs enable their low-speed outputs that is already idling in the J state, then a low-speed packet follows the starting with a sync sequence and PID byte, and ending with a deep period of SE0. Full-speed components other than hubs can simply avoid the PRE packet and its low-speed contents, till the final SE0 indicates that a new packet follows.


Related Discussions:- Data packets - universal serial bus

Explain the term confidentiality - firewall design policy, Explain the term...

Explain the term Confidentiality - Firewall Design Policy Whilst some corporate data is for public consumption, the vast majority of it should remain private.

Explain COMS inverter, Explain CMOS Inverter with the help of a neat circui...

Explain CMOS Inverter with the help of a neat circuit diagram. Ans: CMOS Inverter: The fundamental CMOS logic circuit is an inverter demonstrated in Fig.(a). For above

Performance of pipelines with stalls, Performance of Pipelines with Stalls:...

Performance of Pipelines with Stalls: A stall is reason of the pipeline performance to degrade the ideal performance.                                             Average in

Features and utilities available in java, Explain the features and utilitie...

Explain the features and utilities available in java, which makes it suitable for developing e-commerce applications.     1.  In a network, the transmission of passive informati

Explain about programmable logic array, Q. Explain about Programmable Logic...

Q. Explain about Programmable Logic Array? Until now individual gates are considered as fundamental building blocks from that different logic functions can be derived. With the

Polishing game, Byteland county is very famous for luminous jewels. Luminou...

Byteland county is very famous for luminous jewels. Luminous jewels are used in making beautiful necklaces. A necklace consists of various luminous jewels of particular colour. Nec

Explain transmission gate-based d-latch, The Transmission-Gate input is lin...

The Transmission-Gate input is linked to the D_LATCH data input (D), the control input to the Transmission-Gate is linked to the D_LATCH enable input (EN) and the Transmission-Gate

Explain working of direct memory access, Q. Explain working of Direct Memor...

Q. Explain working of Direct Memory Access? In both programmed I/O and interrupt-driven processor is busy with executing input/output instructions and I/O transfer rate is limi

Explain the virtual memory, In computing, virtual memory is a memory manage...

In computing, virtual memory is a memory management method developed for multitasking kernels. This technique virtualizes computer architecture's various forms of computer data sto

Finite automata, applications of context free grammar

applications of context free grammar

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd