Data packets - universal serial bus, Computer Engineering

Assignment Help:

Data packets:

A data packet consists of the PID which is followed a 16-bit CRC and by 0-1023 bytes of data payload (up to 1024 in high speed and at most 8 at low speed)

There are 2 basic data packets, DATA0 and DATA1. They have to always be preceded by an address token, and are typically followed by a handshake token from the receiver back to the transmitter. The 2 packet types provide the 1-bit sequence number needed by Stop-and-wait ARQ. If a USB host does not retain a response (such as an ACK) for data it has transmitted, it doesn't know if the data was retained or not; the data may have been lost in transit, or it may have been received but the handshake response was lost.

To solve this type of problem, the device keeps track of the type of DATA x packet it last accepted. If it retains another DATA x packet of the similar type, it is acknowledged but ignored as a case of duplicate. Only a DATA x packet of the opposite type is really received.

When a device is reset having a SETUP packet, it expects an 8-byte DATA0 packet next.

USB 2.0 added DATA2 and MDATA packet types as well. They are used just by high-speed devices doing high-bandwidth isochronous transfers which required transferring more than 1024 bytes per 125 µs "micro frame" (8192 kB/s),PRE "packet"

Low-speed components are supported with a special PID value, PRE. It marks the beginning of a low-speed packet, and it is used by hubs which usually do not send full-speed packets to low-speed devices. As all PID bytes include four 0 bits, they leave the bus in the FS(full speed)K state, which is the similar as the low-speed J state. It is followed by a deep pause during which hubs enable their low-speed outputs that is already idling in the J state, then a low-speed packet follows the starting with a sync sequence and PID byte, and ending with a deep period of SE0. Full-speed components other than hubs can simply avoid the PRE packet and its low-speed contents, till the final SE0 indicates that a new packet follows.


Related Discussions:- Data packets - universal serial bus

Explain difference between risc and cisc, RISC-Means Reduced Instruction Se...

RISC-Means Reduced Instruction Set Computer. A RISC system has decreased number of instructions and more significantly it is load store architecture were pipelining can be executed

Declare abstract processor arrays, Think about call of two intrinsic functi...

Think about call of two intrinsic functions discussed above for a 32-Processor (4×8) Multicomputer:    The function call NUMBER_OF_PROCESORS () will return 32.

Explain about physical model, Explain about Physical model The Physical...

Explain about Physical model The Physical model describes concrete software and hardware components of system's context or implementation.

What are the different auto reports available in access, What are the diffe...

What are the different auto reports available in Access? The dissimilar auto reports available in Access are: Columnar AutoReport: makes a report where each row is shown ver

Data hazards in computer architecture, Data hazards -  computer architec...

Data hazards -  computer architecture : A main effect of pipelining is to alter the relative timing of instructions by overlapping their execution. This introduces contro

Explain pure and impure interpreters, Explain Pure and impure interpreters ...

Explain Pure and impure interpreters In a pure interpreter, the source program is retained into the source form all throughout its interpretation. These arrangements incur subs

The field sy-dynr, The field SY-DYNR refers to Number of the current sc...

The field SY-DYNR refers to Number of the current screen.

What is secondary storage systems, There are various limitations of primary...

There are various limitations of primary memory like limited capacity which is its not enough to store a very large volume of data and volatility which is when power is turned off

General registers in a processor, In this segment, we will give very brief ...

In this segment, we will give very brief details of registers of a RISC system known as MIPS. MIPS is a register-to-register or load/store architecture and employs three address

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd