Data packets - universal serial bus, Computer Engineering

Assignment Help:

Data packets:

A data packet consists of the PID which is followed a 16-bit CRC and by 0-1023 bytes of data payload (up to 1024 in high speed and at most 8 at low speed)

There are 2 basic data packets, DATA0 and DATA1. They have to always be preceded by an address token, and are typically followed by a handshake token from the receiver back to the transmitter. The 2 packet types provide the 1-bit sequence number needed by Stop-and-wait ARQ. If a USB host does not retain a response (such as an ACK) for data it has transmitted, it doesn't know if the data was retained or not; the data may have been lost in transit, or it may have been received but the handshake response was lost.

To solve this type of problem, the device keeps track of the type of DATA x packet it last accepted. If it retains another DATA x packet of the similar type, it is acknowledged but ignored as a case of duplicate. Only a DATA x packet of the opposite type is really received.

When a device is reset having a SETUP packet, it expects an 8-byte DATA0 packet next.

USB 2.0 added DATA2 and MDATA packet types as well. They are used just by high-speed devices doing high-bandwidth isochronous transfers which required transferring more than 1024 bytes per 125 µs "micro frame" (8192 kB/s),PRE "packet"

Low-speed components are supported with a special PID value, PRE. It marks the beginning of a low-speed packet, and it is used by hubs which usually do not send full-speed packets to low-speed devices. As all PID bytes include four 0 bits, they leave the bus in the FS(full speed)K state, which is the similar as the low-speed J state. It is followed by a deep pause during which hubs enable their low-speed outputs that is already idling in the J state, then a low-speed packet follows the starting with a sync sequence and PID byte, and ending with a deep period of SE0. Full-speed components other than hubs can simply avoid the PRE packet and its low-speed contents, till the final SE0 indicates that a new packet follows.


Related Discussions:- Data packets - universal serial bus

Explain cache-only memory access model (coma), Cache-Only Memory Access Mod...

Cache-Only Memory Access Model (COMA) As we have considered earlier, shared memory multiprocessor systems can use cache memories with each processor for decreasing the execution

Security, We now consider the relation between passwords and key size. For ...

We now consider the relation between passwords and key size. For this purpose consider a cryptosystem where the user enters a key in the form of a password. Assume a password consi

Presentation of the report, This will be based on presentation of the repor...

This will be based on presentation of the report, complexity of the task, degree of completion and uniqueness of your problem.  As a part of this question, you should also inclu

What is model view controller (mvc), Model-View-Controller (MVC) is a desig...

Model-View-Controller (MVC) is a design pattern in which "the user input, the modelling of the external world and the visual feedback to the user are explicitly splitted and handle

Sorting circuit along with odd-even merging circuit, Q. Sorting Circuit alo...

Q. Sorting Circuit along with Odd-Even Merging Circuit? The merge sort algorithm needs two circuits which imply that one circuit for merging and another circuit for sorting the

Define the types of software life cycle, Define the types of software life ...

Define the types of software life cycle Any system progress refers to the initial part of the software life cycle: analysis, design, and implementation. During object oriented

What are types of firewalls, What are types of firewalls? There are con...

What are types of firewalls? There are conceptually two types of firewalls as: 1. Network Level 2. Application Level

Example on sorting using combinational circuit, Q. Example on Sorting using...

Q. Example on Sorting using Combinational Circuit? Example: Think about a unsorted list having element values like given below {3,9,8,5,10,12,14,20,90,95,60,40,23,35,18,0}

State the selective clear - logic micro operations, State the SELECTIVE CLE...

State the SELECTIVE CLEAR - logic micro operations The selective-clear operation clears to 0 bits in register A only  where there are corresponding 1's in the register B. For

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd