Create a factory function and constructor, Computer Engineering

Assignment Help:

1) This project will use an account class that has the members:

string account_code;

string first_name;

string last_name;

double balance;

Provide a constructor that initializes ALL members in its initialization list with data passed in as arguments to the constructor.  You will also need accessor functions to get the account code and balance and to set the balance.

In addition, include two pure virtual functions that look like the following:

virtual void monthly_update() = 0;

virtual char type() = 0;

2) Design and implement the following derived classes that will inherit from account and implement the monthly_update function in the following manner: 

2058_Create a factory function.png

If the type is an 'X', skip the account record.  In other words, the account should not be processed by the rest of the program and should not appear in the result.

If the type is anything else, throw an invalid_account_type exception (that you will have to write), but DO NOT stop processing the rest of the accounts.  Instead, log the account to a file named "account.log". Trim spaces from the right of the first_name and last_name members.

4) Write a manager class that has a vector member and a main function.  In the main function, open an ifstream on the file, "account2.dat", which will be supplied to you.  If the file does not exist, throw a file_not_found exception (that you will have to write) and terminate the program after logging this to the "account.log" file.

5) For each account in the input file, invoke the factory function/class written in part

3)  Each object returned from the factory function will then be inserted into the vector. 

1874_Create a factory function1.png

If the account is to be ignored, or if the factory function throws an invalid_account_type exception, no account should be inserted into the vector (let alone even created).  At the end of the stream, proceed with part 6.

6) Iterate through the vector and invoke the monthly_update function for each account in the vector.

7) Using an ofstream, output each account to a new file named "update.dat" in the SAME format as "account2.dat".

8) Output the accounts in a "human readable format" to a file, "report.txt".  The output format is of your choice, but please include all the members of each account per line (including the type).

9) Write a main function that instantiates your manager class from part 4, invokes its main and takes care of any exceptions that could possibly "leak" out.


Related Discussions:- Create a factory function and constructor

Which is the best tool for monitoring weblogic server(wls8), WLS8 handles J...

WLS8 handles JMX but it uses weblogic execution of JMX server. It does not supports generalise sun javax API which can be used with any JVM. There are some patches available which

What is ai backgammon, This part looks at Berliner's program, two backprop ...

This part looks at Berliner's program, two backprop versions by Tesauro and a temporal difference process by Tesauro. This latter program is VERY good quality and has found strateg

How much frequency is centered in typical human voice, Typical human voice ...

Typical human voice is centered around                   Hz. (A)  200-400                                     (B)  280-3000  (C)  400-600

What is core dump, Raises when accessing an unassigned memory location acce...

Raises when accessing an unassigned memory location accessing a null pointer

What is socket, A socket is one end-point of a two-way communication link a...

A socket is one end-point of a two-way communication link among two programs running on the network. Socket classes are used to show the connection among a client program and a ser

Example on multi-statement forall construct, Q. Example on Multi-statement ...

Q. Example on Multi-statement FORALL construct? The subsequent statements set every element of matrix X to sum of its indices.  FORALL (i=1:m, j=1:n)      X(i,j) = i+j an

How do we synthesize verilog into gates with synopsys, How do we synthesize...

How do we synthesize Verilog into gates with Synopsys?  The answer can, of course, occupy various lifetimes to completely answer.. BUT.. a straight-forward Verilog module can b

Explain about end-user computing, End-user Computing: The growing base of p...

End-user Computing: The growing base of personal computers and local area networks in the end user community are supported. This offers installation services, training and helps de

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd