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The logic circuit shown in the given figure can be minimised to
Ans. The minimised figure of logic diagram is D, the output of the logic circuit is as
Y=(X+Y')'+(X'+(X+Y')')' (X+Y')'=X'Y
By using DE Morgan's here it is one of input of 2nd gate.
F=(A+X')'=A'X=[(X'Y)'.X]=[(X+Y')X]=X+XY'=X(Y')=X
Will case infer priority register if yes how give an example? Yes case can infer priority register depending on coding style reg r; // Priority encoded mux, always @
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Find out the two inputs when the NAND gate output will be low. Ans. The output of NAND gate will be low if the two inputs are 11. The Truth Table of NAND gate is shown
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Overriding tell us only the methods, but shadowing tells us the entire element.
how to implemr
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