Configure port to send logic, Computer Engineering

Assignment Help:

Configure port A for the lower 4 bits to be inputs and the upper 4 bits to be outputs. The program should chase a logic one from Pa4 -> Pa7, depending upon the condition of Pa0-Pa3 the speed of chase is increased.

Pa0  = 1  Slow Counter  
Pa1  = 1  Counter   
Pa2  = 1  Counter    
Pa3  = 1  Fast  Counter    
 
If all Pa0, Pa1, Pa2, Pa3 = 0 wait
 
The only major difference is the data direction i.e. this configures 4 input lines Pa0-Pa3 and 4 output lines Pa4-Pa7

Paddr
Bit7  Bit6  Bit5  Bit4  Bit3  Bit2  Bit1  Bit0
1  1  1  1  0  0  0  0
 
The full program is shown below

                  name first
padr          equ $0000
paddr        equ $0001
                 org $500
                 ldaa #$f0
                 staa paddr     set up half in and half out
loop0        ldaa #$10
                 staa padr     send data
                 jsr delay
                 ldaa #$20
                 staa padr     send data
                 jsr delay 
                ldaa #$40
                staa padr     send data
                jsr delay
                ldaa #$80
                staa padr     send data
                jsr delay
                jmp loop0
delay        ldab padr    ;get input from port a
                andb #$0f    ;mask of lower nibble only

                beq delay    ;repeat till selected
                ldab padr    ;get port a data again
                andb #$8    ; mask off bit 3 pa3
                bne loop3    ;if select go to loop3
                ldab padr    ;get port a data again
                andb #$4    ; mask off bit 2 pa2
                bne loop4    ;if select go to loop4
                ldab padr    ;get port a data again
                andb #$2    ; mask off bit 1 pa1
                bne loop5    ;if select go to loop5
                ldx #$ffff    ;assume pa0 is pressed load up x with ffff
                jmp loop1    ;carry on
loop2        ldx #$1    ;load up X with 1 fast
                jmp loop1    ;carry on
loop3        ldx #$f      ;load X with f
                jmp loop1
loop4       ldx #$ff    ;load x with ff
               jmp loop1
loop5      ldx #$fff    ;load x with fff slow
loop1      ldab #$1f    ;nested loop
loop6      decb
              bne loop6
              dex
             bne loop1    ;loop till zero
             rts               ;return back to main
             end


Related Discussions:- Configure port to send logic

Explain about end-user computing, End-user Computing: The growing base of p...

End-user Computing: The growing base of personal computers and local area networks in the end user community are supported. This offers installation services, training and helps de

Forward checking - artificial intelligence, Forward checking: Whether ...

Forward checking: Whether to add some sophistication to the search method there constraint solvers use a technique called as forward checking. So here the general idea is to w

Power and energy, Ask questiPower and EnergyQuestion 4Consider a processor ...

Ask questiPower and EnergyQuestion 4Consider a processor that runs at 2.5 GHz and 1 Volt. When running a given CPU-bound program,the processor consumes 100 W, of which 20 W is leak

Explain transmission gate-based d-latch, The Transmission-Gate input is lin...

The Transmission-Gate input is linked to the D_LATCH data input (D), the control input to the Transmission-Gate is linked to the D_LATCH enable input (EN) and the Transmission-Gate

Construct the finite automata, Give the regular expression of the set of al...

Give the regular expression of the set of all even strings over the alphabet {a, b} along with at least one of the two substrings aa or bb. As well construct the finite automata wh

Describe five bit even parity checker, Describe five bit even parity checke...

Describe five bit even parity checker. Ans: Five bit even parity checker: EX-OR gates are utilized for checking the parity as they generate output 1, while the input ha

Produce a sequence diagram for the task add, This assignment is based on th...

This assignment is based on the 'Swansea Docklands Heritage Society' case study attached.  The assignment is the third of three related submissions, all based on the Swansea Dockla

Define bus, Define bus A group of lines that serves as a connecting pat...

Define bus A group of lines that serves as a connecting path for various devices is known as a bus.

Define a B- tree of order m, Define a B tree of order m. B Tree of orde...

Define a B tree of order m. B Tree of order m  A balanced multiway search tree of order m in which every non root node having at least m/2 keys is known as a B-Tree of order

Chains of inference, Chains of Inference: Now we have to look at how t...

Chains of Inference: Now we have to look at how to get an agent to prove a given theorem using various search strategies? Thus we have noted in previous lectures that, there i

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd