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Q. D flip-flop - latch or delay element? The symbol for the clocked D flip-flop is shown in Figure (a), in which the two output terminals Q and ¯ Q behave just as in the SRFF,
Q. What are the features of clamping circuits? The clamping circuit does not change the peak to peak or r.m.s value of the waveform .Thus the input waveform and clamped output
how to construct universal shift register using D-flipflop and mux??
Three transformers are provided with the following rating values: 1) 2400/240 V, 55kVA, Req1 = (0.1 + 0.0Y) Ohm and Xeq1 = (0.15 + 0.XX) Ohm. 2) 240/120 V, 25kVA, Req1 = (0.1
Q. An 8-bit A/D converter is driven by a 1-MHz clock. Estimate the maximum conversion time if: (a) It is a counter-controlled A/D converter. (b) It is a successive-approximat
Q. Required Conditions for connecting two transformers in parallel? Ans: a) Voltage rating should be same b) Per unit impedance should be same c) Phase sequence should
BLOCK DIAGRAM OF DIGITAL CONTROL OF ELECTRIC DRIVES
Define voltage divider rule Voltage drop at every resistor that connected by serial can be search by using voltage divider rules (VDR).
Nodes analysis Analysis using KCL to solve for voltages at every common node of the network and as determines the currents by and voltages across every elements of the network.
A pure sine wave with a frequency of 100Hz is sampled at 150Hz. At which one of the following frequencies would you expect an alias?
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