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Compare memory mapped I/O with I/O mapped I/O.
Memory Mapped I/O Scheme: In this scheme there is only one address space. Address space is stated as all possible addresses that microprocessor can generate. Some addresses are allocated to memories and some addresses to I/O devices. An I/O device is also treated just like a memory location and one address is assigned to it. In this scheme all the data transfer instructions of microprocessor can be used for both memory and I/O device. This scheme is suitable for a small system.
In I/O mapped I/O scheme addresses assigned to memory locations can also be assigned to I/O devices. As the same address may be assigned to a memory location or an I/O device, microprocessor should issue a signal to distinguish whether the address on address bus is for a memory location or an I/O device.
Prove the following Boolean identities using the laws of Boolean algebra (A + B)(A + C) = A + BC Ans. (A+B)(A+C)=A+BC LHS AA+AC+AB+BC=A+AC+AB+BC OR A((C+1)+A(B+1))+BC
The NOR gate. The NOR gate is equivalent to an OR gate followed by a NOT gate so that the output is at logic level 0 when any of the inputs are high otherwise it is at logic le
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Write the truth table of NOR gate. Ans. The truth table for NOR gtae is shown below:
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Define Top-down parsing Techniques Top-down parsing can be observed as an attempt to find left-most derivations of an input-stream through searching for parse trees using a top
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