Cmp-arithmetic instruction-microprocessor, Assembly Language

Assignment Help:

CMP: Compare: - This instruction compares the source operand, which can be a register or memory location an immediate data with a destination operand that might be a register or a memory location. For the purpose of comparison, it subtracts the  source  operand  from  the destination  operand  but does  not stock up the result anywhere. The flags are affected and depending on the result of the subtraction. If both of the operands are equal to zero flag is set. If the source operand is higher than the destination operand, carry flag is set or else is reset. The instance of this instruction are following:

Example :

1. CMP      BX,         0100H          Immediate

2. CMP      0100                          Immediate [AX implicit]

3. CMP      [5000H],OIOOH          Direct

4. CMP      BX,         [SI]               Register indirect

5. CMP      BX,         CX                Register

 


Related Discussions:- Cmp-arithmetic instruction-microprocessor

8254 programmable timer-microprocessor, 8254 Programmable Timer A diagr...

8254 Programmable Timer A diagram of Intel's 8254 interval event/timer counter is given in Figure. The 8254 consists of 3 identical counting circuits, per of which has GATE and

Add-arithmetic instruction-microprocessor, ADD:  Add :- This instruction ...

ADD:  Add :- This instruction adds an immediate contents of a memory location specified in the a register ( source ) or instruction to the contents of another register (destinat

Hex , what is the hex value in ax after executing the instructions ax= 1E8...

what is the hex value in ax after executing the instructions ax= 1E8A bx=4080 add al,bl sub ah,bh

PIC lights on, errorlevel -302 ;prevents error code for this...

errorlevel -302 ;prevents error code for this chipset __config 0x373A ;chip config PIC spec page 146 processor 16F877A ;chipset reset code

Format of control register-microprocessor, Format of Control Register T...

Format of Control Register The format for the control register is given in Figure. Bit 0 of this register might be one before data may be output  and  bit  two  might be  one

Cache controller-microprocessor, Cache controller The cache controller ...

Cache controller The cache controller is the mind of the cache.  Its responsibilities include:  performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing

Hold response sequence-microprocesssor, Hold Response Sequence The HOLD...

Hold Response Sequence The HOLD pin is examined at leading edge of each clock pulse. If it is received active line by the processor before T4 of the earlier cycle/during the T1

First generation microprocessor, 1 st Generation Microprocessor : At ...

1 st Generation Microprocessor : At the end of the 70s a group of engineers developed a chip is able to processing data. This chip was called processor chip. Big processors w

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd