Cache components-microprocessor, Assembly Language

Assignment Help:

Cache components

The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multiple chips or all can be combined into a single chip.

SRAM :

SRAM (Static Random Access Memory) is memory block which holds the data and the size of the SRAdetermines the size of the cache.

Tag RAM :

Tag RAM (TRAM)  is a small part of SRAM that stores the addresses  of the data that is stored in theSRAM.

Cache controller :

The cache controller is the mind of the cache. Its responsibilities include: performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing  the write policy.  Also the cache controller is responsible fordetermining if memory request is cacheable  and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The  bits of the status register can be used to signal to the processor.

The cache controller accepts commands from the processor. Following are the examplesof the commands are

  • Reset the Tag Rams
  • Set interrupt mask

 

The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It  is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.

 


Related Discussions:- Cache components-microprocessor

Microprocessor, from pin description it seems that 8086 has 16 address/data...

from pin description it seems that 8086 has 16 address/data lines i.e.AD0_AD15.The physical address is however is larger than 2^16.How this condition can be handled

Cmps-string manipulation instruction-microprocessor, CMPS : Compare String...

CMPS : Compare String Byte or String Word:-The CMPS instruction may be utilized to compare two strings of Words or byte. The length of the string ought to be stored in the CX. If

Xml, Write the structure of For…Next loop in VB.Net and also write a progra...

Write the structure of For…Next loop in VB.Net and also write a program to print integers from 1 to 10 on the console.

Interrupt table-how interrupt table processed-microprocessor, Interrupt Tab...

Interrupt Table Each interrupt level has a booked memory location, called an interrupt vector.  All these vectors (or pointers) are stored in the interrupt table. Table lies at

Compute the fibonacci sequence - assembly program, Compute the Fibonacci se...

Compute the Fibonacci sequence - assembly program: Problem: Fibonacci   In this problem you will write a program that will compute the first 20 numbers in the Fibonacci sequ

Read architecture:look through-microprocessor, Read Architecture: Look Thro...

Read Architecture: Look Through Main memory that located is conflicting the system interface. The least concerning feature of this cache unit is that it remain between the proc

Group-assemblers directive-microprocessor, GROUP : Group the Related Segme...

GROUP : Group the Related Segments:- The directive which is used to form logical groups of segments with same purpose or type. This isused to inform the assembler to form a log

Pin functions of 8086-microprocessor, Pin functions for the minimum mode o...

Pin functions for the minimum mode operation of 8086 are following: 1) M/I/O -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it

Icwi-microprocessor, The definitions of the bits in ICWI are following: ...

The definitions of the bits in ICWI are following: Always set to the value 1. It directs the received byte to ICWI as oppose to OCW2 or OCW3. Which also utilize the even addr

Project, I need some guidance on which project to make in assembly language...

I need some guidance on which project to make in assembly language

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd