Cache components-microprocessor, Assembly Language

Assignment Help:

Cache components

The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multiple chips or all can be combined into a single chip.

SRAM :

SRAM (Static Random Access Memory) is memory block which holds the data and the size of the SRAdetermines the size of the cache.

Tag RAM :

Tag RAM (TRAM)  is a small part of SRAM that stores the addresses  of the data that is stored in theSRAM.

Cache controller :

The cache controller is the mind of the cache. Its responsibilities include: performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing  the write policy.  Also the cache controller is responsible fordetermining if memory request is cacheable  and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The  bits of the status register can be used to signal to the processor.

The cache controller accepts commands from the processor. Following are the examplesof the commands are

  • Reset the Tag Rams
  • Set interrupt mask

 

The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It  is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.

 


Related Discussions:- Cache components-microprocessor

Pointer and index registers-microprocessor, Pointer and Index Registers ...

Pointer and Index Registers The pointers contain offset within the specific segments. The pointers BP, IP and SP generally containoffsets within thedata, code and stack segment

Matrices, code to add two matrices

code to add two matrices

Shr-sar-logical instruction-microprocessor, SHR : Shift Logical Right: Thi...

SHR : Shift Logical Right: This instruction performs bit-wise right shifts on the operand word or byte that might be reside in  a memory location or a register, by the specified c

input and output, Description: LC3 allows input from keyboard and out...

Description: LC3 allows input from keyboard and output to display on the screen. This lab will exercise the input/output capability using LC-3 Assembly language. Procedure

I want to make a calculator, 64-bit integer calculator, which processes usi...

64-bit integer calculator, which processes using 16-bits at a time (reg/mem16 operands)

#title, how i can write a program to divide 2 numbers

how i can write a program to divide 2 numbers

Cisc characteristics-microprocessor, CISC Characteristics : The design...

CISC Characteristics : The design of an instruction  set for a computer  might take into consideration  not only machine language constraints,  but  also  the  requirements  i

Memory interface-microprocessor, Memory Interface              ...

Memory Interface                                                                  Figure: Memory Modulation design The memory of a computer contain of number of memo

Al registre, check the al-register for palindromic number

check the al-register for palindromic number

Memory address decoding-microprocessor, Memory Address Decoding Binary ...

Memory Address Decoding Binary Decoders - Decoders have 2n-inputs and n outputs, each input combination results in a single output line contain a 1, and all other lines contain

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd