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Cache components
The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented by multiple chips or all can be combined into a single chip.
SRAM :
SRAM (Static Random Access Memory) is memory block which holds the data and the size of the SRAdetermines the size of the cache.
Tag RAM :
Tag RAM (TRAM) is a small part of SRAM that stores the addresses of the data that is stored in theSRAM.
Cache controller :
The cache controller is the mind of the cache. Its responsibilities include: performing the snarfs and snoops, updating the TRAM and SRAM and implementing the write policy. Also the cache controller is responsible fordetermining if memory request is cacheable and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The bits of the status register can be used to signal to the processor.
The cache controller accepts commands from the processor. Following are the examplesof the commands are
The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.
Write a program to merge two sorted arrays to create a third sorted array containing all values from the two original arrays. Merge is a key component to the mergesort algorithm.
INTO : Interrupt on Overflow:- It is executed, when the overflow flag OF is set. The new contents of IP and CS register are taken from the address 0000:0000 as described in INT
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General terms for Cache : Cache Hits : When the cache consisted the information requested, the transaction is said to be a cache hit. Cache Miss : When the cache does n
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