Cache components-microprocessor, Assembly Language

Assignment Help:

Cache components

The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multiple chips or all can be combined into a single chip.

SRAM :

SRAM (Static Random Access Memory) is memory block which holds the data and the size of the SRAdetermines the size of the cache.

Tag RAM :

Tag RAM (TRAM)  is a small part of SRAM that stores the addresses  of the data that is stored in theSRAM.

Cache controller :

The cache controller is the mind of the cache. Its responsibilities include: performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing  the write policy.  Also the cache controller is responsible fordetermining if memory request is cacheable  and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The  bits of the status register can be used to signal to the processor.

The cache controller accepts commands from the processor. Following are the examplesof the commands are

  • Reset the Tag Rams
  • Set interrupt mask

 

The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It  is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.

 


Related Discussions:- Cache components-microprocessor

Write program that will generate array of ten random number, 1. Write a pro...

1. Write a program that will generate an array of ten random 32-bit integers, and that will  display on the monitor the numbers followed by either the words " has the fourth bit se

8086 assembly language, write and run a programme using 8086 assembly langu...

write and run a programme using 8086 assembly language that interchange the lower four bits of AL registered with upper four bits.

Modes of 8254-microprocessor, Modes of 8254 :   Mode 0 (Inter...

Modes of 8254 :   Mode 0 (Interrupt on Terminal Count)-GATE which value is 1 enables counting and GATE  which value is 0 disables counting, and GATE put not effect on

Pin description of 8086-microprocessor,  Pin Description of 8086 The ...

 Pin Description of 8086 The microprocessor 8086 is a 16-bit CPU available in 3 clock rates, for example 5, 8 and 10 MHz, packaged in a40 pin CERDIP or plastic package. The 8

Cache controller-microprocessor, Cache controller The cache controller ...

Cache controller The cache controller is the mind of the cache.  Its responsibilities include:  performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing

#title., BINARY TO GRAY CONVERSION

BINARY TO GRAY CONVERSION

Program, Write a program to separate out positive and negative numbers from...

Write a program to separate out positive and negative numbers from a given series of 16-bit hexadecimal numbers.

Assigment help, assempbly language routine that takes an array named A cont...

assempbly language routine that takes an array named A containing n bytes of postive numebrs and fills two arranys, array B containing n words and array C containing n long words

input and output, Description: LC3 allows input from keyboard and out...

Description: LC3 allows input from keyboard and output to display on the screen. This lab will exercise the input/output capability using LC-3 Assembly language. Procedure

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd