Cache components-microprocessor, Assembly Language

Assignment Help:

Cache components

The cache sub-system may be divided into 3 functional blocks: Tag RAM, SRAM and theCache Controller. In real designs, these blocks can be implemented  by multiple chips or all can be combined into a single chip.

SRAM :

SRAM (Static Random Access Memory) is memory block which holds the data and the size of the SRAdetermines the size of the cache.

Tag RAM :

Tag RAM (TRAM)  is a small part of SRAM that stores the addresses  of the data that is stored in theSRAM.

Cache controller :

The cache controller is the mind of the cache. Its responsibilities include: performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing  the write policy.  Also the cache controller is responsible fordetermining if memory request is cacheable  and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The  bits of the status register can be used to signal to the processor.

The cache controller accepts commands from the processor. Following are the examplesof the commands are

  • Reset the Tag Rams
  • Set interrupt mask

 

The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It  is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.

 


Related Discussions:- Cache components-microprocessor

Operating System, Why is the capability to relocate processes desirable?

Why is the capability to relocate processes desirable?

Port mapped or mapped input output, Port Mapped I/O or I/O Mapped I/O I...

Port Mapped I/O or I/O Mapped I/O I/O devices are mapped into a separate address space. This is generally accomplished by having a different set of signal lines to denote a mem

Rep-string manipulation instruction-microprocessor, REP : Repeat Instructi...

REP : Repeat Instruction Prefix :- This instruction is utilized as a prefix to other instructions. The instruction in which the REP prefix is provided, is executed repetitively

Cmp-arithmetic instruction-microprocessor, CMP: Compare: - This instructio...

CMP: Compare: - This instruction compares the source operand, which can be a register or memory location an immediate data with a destination operand that might be a register or a

Program to perform a conversion on characters in a text file, Write an asse...

Write an assembly language program to perform a rot13 1 conversion on characters in a text file.  The program should read charatcers from the input file, perform the rot13 convers

Interrupt system based on 8259 a-microprocessor, Interrupt System Based on ...

Interrupt System Based on Single 8259 A The 8259A is contained in a 28-pin dual-in-line package that need only a + 5-V supply voltage.  Its organization is shown in given figur

8088 timing system diagram-Microprocessor, 8088  Timing System Diagram ...

8088  Timing System Diagram The 8088 address/data  bus is divided  in 3 parts (a) the lower 8 address/data  bits, (b) the middle 8 address bits, and (c) the upper 4 status/

The pentium pro-micro processor, The Pentium Pro    Introduced in the ...

The Pentium Pro    Introduced in the year 1995, the Pentium Pro reflected  still  more  design  breakthroughs.  The Pentium Pro may process 3 instructions in a single clock cy

Internal architecture of microprocessor, Internal Architecture of Microproc...

Internal Architecture of Microprocessor : The architecture of 8086 provides a number of improvements over 8085 architecture. It supports a, a set of 16-bit registers ,16-bit AL

Addressing modes for sequential control-microprocessor, The addressing mode...

The addressing modes for the sequential control transfer instructions are described below:   1. Immediate: Immediate data is a part of instruction,in this type of addressin

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd