Buses - computer architecture, Computer Engineering

Assignment Help:

Buses:

  • Execution of 1 instruction need the following 3 steps to be performed by the CPU:

I.  Fetch the contents of the memory location pointed at by the computer system. The contents of this location are interpreted as an instruction to be executed. Therefore, they are holed up in the instruction register (IR). Symbolically, it can be written as:

1438_Buses.png

2. supposing that the memory is byte addressable .it increment the contents of the PC by 4, that is 1155_Buses1.png

3.   Perform the actions mention by the instruction stored in the IR

  • But, in cases wherever an instruction take place more than 1 word, steps 1 and 2 might be repeated as several times as essential to fetch the complete instruction.
  • 2 first steps are typically referred to as the fetch phase.
  • Step 3 constitutes  in the execution phase

 

29_Buses2.png

Most of the operation in step 1 to 3 denoted earlier can be carried out by performing one or more of the following function

However, in cases where an instruction takes place more than 1 word, steps 1 and 2 might be

repeated as several times as essential to fetch the complete instruction.

  • 2 first steps are usually referred to as the fetch phase.
  • Step 3 constitutes in the execution phase

Fetch the contents of a specific memory location and load them into a CPU Register

  • Hold up a word of data from a CPU register into a particular given memory location.
  • Transfer a word of data from 1 CPU register to another or to ALU.
  • Perform logic or arithmetic operation, and store the outcome in a CPU register.

 


Related Discussions:- Buses - computer architecture

Is the data bus is bi-directional, The data bus is Bi-directional because t...

The data bus is Bi-directional because the similar bus is used for transfer of data among Micro Processor and memory or input / output devices in both the direction.

Direct addressing and immediate addressing mode , Direct Addressing and  I...

Direct Addressing and  Immediate Addressing mode - computer architecture:  Immediate Addressing: It is the simplest form of addressing. Here, the operand is itself given

Explain direct or indirect communication, Explain Direct or Indirect Comm...

Explain Direct or Indirect Communication in Inter-process communication. Several types of message passing system in Direct or Indirect Communication are given below:

Total number of registers in a cpu, Q. Total number of registers in a CPU? ...

Q. Total number of registers in a CPU? Factors to consider when choosing total number of registers in a CPU are:  CPU can access registers faster than it can access m

Board coloring, In this problem you are given a board in which some of the...

In this problem you are given a board in which some of the elements are placed as shown in diagram below. Each element represents a color. Fill the other elements in the board, suc

Explain scientific applications and image processing, Scientific Applicatio...

Scientific Applications/Image processing Major of concurrent processing applications from science and other academic disciplines, are mostly have based on numerical simulations

What is spread spectrum, Question: (a) In order to encourage the develo...

Question: (a) In order to encourage the development mobile technologies, Europe has opted for standardisation. What is the rationale behind this? Provide concrete examples of h

Define arithmetic pipelines, Arithmetic Pipelines The technique of pipe...

Arithmetic Pipelines The technique of pipelining can be applied to various complex and low arithmetic operations to speed up processing time. Pipelines used for arithmetic calc

What is the function of a tlb, What is the function of a TLB (translation...

What is the function of a TLB (translation look-aside buffer)? A small cache called the TLB is interporated into MMU, which having of the page table entries that correspondi

What do you mean by daisy chain, Q. What do you mean by Daisy chain? Th...

Q. What do you mean by Daisy chain? This scheme provides a hardware poll. With this scheme, an interrupt acknowledge line is chain by different interrupt devices. All I/O inter

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd