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Bubbling the Pipeline:
Bubbling the pipeline (also known as a pipeline break or pipeline stall) is a technique for preventing, structural, data and branch hazards from taking place. As instructions are fetched, control logic determines whether a hazard could/will take place. If they can, then the control logic inserts NOPs instruction into the pipeline. Therefore, before the next instruction (which is reason of the hazard) is executed, the previous 1 will have had adequate time to complete and prevent the hazard. If the number of NOPs is equivalent to the number of stages in the pipeline, the processor has been cleared of all of the instructions and can proceed free from hazards. It is called flushing the pipeline. All forms of stalling introduce a delay before the processor may resume execution.
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Static memories Circuits capable of receiving their state as long as power is applied volatile Static RAM(SRAM)
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