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Within micro controller's software, it is very useful to be able to manipulate binary bits i.e. from ports etc. The ALU has command to shift data, rotate data, compare data, set/clear bits, test bits and logical operate on data.
LSLA i.e shift A one place to the left fill up with 0 LSLB i.e shift B one place to the left fill up with 0 LSRA i.e shift A one place to the right fill up with 0 LSRB i.e shift B one place to the right fill up with 0 ROLA i.e rotate A one place to the left through carry ROLB i.e rotate B one place to the left through carry RORA i.e rotate A one place to the right through carry RORB i.e rotate B one place to the right through carry CBA i.e A-B with no answer stored just flags set CMPA i.e compare A with memory i.e A-M CMPB i.e compare B with memory i.e B-M BSET $20,#$1 i.e set bit 1 of memory address 20 BCLR $20,#$1 i.e clear bit 1 of memory address 20 BITA $20 i.e Check bit mask found in A with address 20 BITB $20 i.e Check bit mask found in A with address 20 ANDA $20 i.e logical and A with data at address 20 EXORA $20 i.e logical exor A with data at address 20 COM $20 i.e logical invert data at address 20 ORRA $20 i.e logical OR A with data at address 20 MUL ;Multiplies axb and stores the answer in D i.e both FDIV ;Fractional divide using D/IX IDIV ;Integer divide using D/IX ADDD ;16 bit add to D DAA ;Decimal adjust add sum to BCD data
#write a program to find the area under the curve y=f(x) between x =a and x=b integrate the area between a and b by c programming
Define device interface. The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are part of circuitry commonly called as a device interface.
reflection in 2d
Processor-Memory Interconnection Network (PMIN) This is a switch that joined various processors to different memory modules. Connecting every processor to each memory module in
example pumping lemma.
What''s is a lissajious pattern?
Classification according to pipeline configuration: According to the configuration of a pipeline, the following parts are recognized under this classification: Unifunct
Q. Design issues of Multi-threaded processors? To accomplish the maximum processor utilization in a multithreaded architecture, the subsequent design issues should be addressed
What are the characteristics of SRAM? SRAM are fast They are volatile They are of high cost Less density
Commutatively of Connectives You will be aware from the fact that some arithmetic operators have a property that it does not matter which way around you give the operator input
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